{"title":"Use of the Myers-Briggs type indicator in an undergraduate microelectronics course","authors":"R. E. Pearson, A. Bell, J.R. Croley","doi":"10.1109/UGIM.2003.1225715","DOIUrl":"https://doi.org/10.1109/UGIM.2003.1225715","url":null,"abstract":"This paper presents the results of five years of administering the Myers-Briggs type indicator (MBTI) to electrical engineering students in a junior level course at Virginia Commonwealth University. The goal was to promote student awareness of the diversity of personality types and at the same time challenge them to use this knowledge in a team design project. This evaluation process and lecture on the MBTI was done with industrial support and is a good example of University Industry cooperation. The results presented are similar to previously reported type distributions for engineering students but it is the use of the type information for team formation that is unique. A summary of anecdotal findings is given to indicate how this effort has been useful beyond the numerical findings.","PeriodicalId":356452,"journal":{"name":"Proceedings of the 15th Biennial University/Government/ Industry Microelectronics Symposium (Cat. No.03CH37488)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121104759","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Fabrication of an MOS Capacitor structure at NGEE ANN POLYTECHNIC's IC fabrication facility","authors":"M. Philip","doi":"10.1109/UGIM.2003.1225755","DOIUrl":"https://doi.org/10.1109/UGIM.2003.1225755","url":null,"abstract":"This paper describes an attempt to build and test MOS Capacitor structures at NGEE ANN POLYTECHNIC. This project was undertaken by a group of students. Details of the process flow and test strategies utilized are provided. Problems encountered and solutions taken are reported. The impact of the exercise on student learning is assessed.","PeriodicalId":356452,"journal":{"name":"Proceedings of the 15th Biennial University/Government/ Industry Microelectronics Symposium (Cat. No.03CH37488)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127285463","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"In-situ depth monitoring of the deep reactive ion etch process","authors":"Y. Imura, B.X. Li, K. Farmer","doi":"10.1109/UGIM.2003.1225775","DOIUrl":"https://doi.org/10.1109/UGIM.2003.1225775","url":null,"abstract":"We describe a laser-based technique to monitor the time multiplexed deep reactive ion etching of silicon. Mask and substrate etch rates, as well as mask quality information, can be extracted simultaneously and in-situ using a single laser beam system.","PeriodicalId":356452,"journal":{"name":"Proceedings of the 15th Biennial University/Government/ Industry Microelectronics Symposium (Cat. No.03CH37488)","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130538658","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A 435 MHz high-gain low-power LNA in 0.35 /spl mu/m SOI CMOS","authors":"D. Huang, E. Zencir, N. Dogan, E. Arvas","doi":"10.1109/UGIM.2003.1225709","DOIUrl":"https://doi.org/10.1109/UGIM.2003.1225709","url":null,"abstract":"A low-power, high-gain, fully-differential low noise amplifier (LNA) in 0.35 -/spl mu/m SOI CMOS technology is designed and tested. The LNA is intended for use as the amplification stage in a subsampling receiver at UHF frequency. The measured 46-dB small signal gain, 3-dB noise figure, and 19-mW total power consumption is reported for the first time.","PeriodicalId":356452,"journal":{"name":"Proceedings of the 15th Biennial University/Government/ Industry Microelectronics Symposium (Cat. No.03CH37488)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126678487","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"SU-8 as an electron beam lithography resist","authors":"F. Williamson, E. Shields","doi":"10.1109/UGIM.2003.1225696","DOIUrl":"https://doi.org/10.1109/UGIM.2003.1225696","url":null,"abstract":"SU-8 resist is an epoxy resin dissolved with a photoinitiator in an organic solvent. The result is a negative resist originally developed for high aspect ratio MEMS applications. For some applications SU-8 has several advantages over the most commonly used e-beam resist, PMMA, which include a much higher sensitivity and increased chemical and mechanical robustness. We have used our Raith 150 electron beam lithography tool to investigate SU-8 in two different applications. First, we investigated the properties of a specially formulated SU-8 which can be spun as thin as /spl sim/100 nm. This is much thinner than normal formulations but necessary for high-resolution lithography. We then exposed an array of single pixel lines with a pitch of 200 nm. At a dose of 30 pC/cm we obtained a line width of /spl sim/60 nm. Second, using standard formulations of SU-8, we discovered that films as thick as 8 microns can be exposed with a 30 kV electron beam, the maximum of our system. Using the contrast curve as a calibration reference, we were able to make analog three-dimensional structures by spatially varying the dose as the feature is being written. With this technique we fabricated a 3/spl times/3 array of f/9 spherical lenses.","PeriodicalId":356452,"journal":{"name":"Proceedings of the 15th Biennial University/Government/ Industry Microelectronics Symposium (Cat. No.03CH37488)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129030357","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Overview of fully depleted silicon-on-insulator (SOI) technology","authors":"P. T. Tran","doi":"10.1109/UGIM.2003.1225771","DOIUrl":"https://doi.org/10.1109/UGIM.2003.1225771","url":null,"abstract":"This paper examines the advantages and disadvantages of thin-film, fully depleted (FD) silicon-on-insulator (SOI) technology devices compared to bulk devices, describing their desirability and suitability for low-voltage and low-power very large-scale integrated (VLSI) circuits.","PeriodicalId":356452,"journal":{"name":"Proceedings of the 15th Biennial University/Government/ Industry Microelectronics Symposium (Cat. No.03CH37488)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128178321","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"An electronic wafer traveler system for an academic microchip fabrication facility","authors":"A. Sheikh, S. Sheetz, R. Hendricks","doi":"10.1109/UGIM.2003.1225774","DOIUrl":"https://doi.org/10.1109/UGIM.2003.1225774","url":null,"abstract":"Even in a university microchip fabrication facility, the process by which bare silicon wafers are transformed into wafers with working devices consists of a complex sequence involving many steps, each of which must be performed by the students precisely as designed by the instructor. In order to assure such processing conformance, each wafer is accompanied by a \"wafer traveler\" that tells the student exactly what to do. These travelers have historically been paper documents. In an attempt to model modern commercial fabrication facilities, and in order to provide electronic data to the students for use in their laboratory reports, we are developing an electronic wafer traveler system (EWTS). This system accomplished two main user functions. First, it allows instructors to develop wafer travelers specific to a given process flow, and second, it produces wafer travelers for that process that will allow students to electronically record and use all data associated with fabricating a wafer by the given process. This paper presents the design of the EWTS using advanced object-oriented software engineering techniques such as use case modeling to show how users interact with the system and class diagramming that shows the structural relationships among data elements as required by the Unified Modeling Language (UML). The resulting third normal form data model will be implemented in SQL 2000 and interfaced to the existing laboratory information management system (LIMS) now in use in our facility. User interaction with the EWTS will be via Visual Basic and Active Server pages using SQL.","PeriodicalId":356452,"journal":{"name":"Proceedings of the 15th Biennial University/Government/ Industry Microelectronics Symposium (Cat. No.03CH37488)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130236363","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Application for WLP at positive working photosensitive polybenzoxazole","authors":"T. Hirano, K. Yamamoto, K. Imamura","doi":"10.2494/PHOTOPOLYMER.15.173","DOIUrl":"https://doi.org/10.2494/PHOTOPOLYMER.15.173","url":null,"abstract":"A positive working photosensitive polybenzoxazole (PBO) for use as a semiconductor surface coating material has been developed. This material has been widely used as a buffer coating to protect electrical circuitry on IC chips in the semiconductor market. We have now developed a new positive working photosensitive PBO for Wafer Level Packaging (WLP). These cured PBO films have very low water absorption and low dielectric constant in addition to high adhesion to a wide range of substrates including SiO2, etc. Additionally, the patterned profile of the developed and cured film has the desired taper shape, which makes these materials suitable as the interlayer dielectric film for WLP.","PeriodicalId":356452,"journal":{"name":"Proceedings of the 15th Biennial University/Government/ Industry Microelectronics Symposium (Cat. No.03CH37488)","volume":"82 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134022586","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
S. Terry, B. Blalock, J. Jackson, Suheng Chen, M. Mojarradi, E. Kolawa
{"title":"Development of robust analog electronics at the University of Tennessee for NASA/JPL extreme environment applications","authors":"S. Terry, B. Blalock, J. Jackson, Suheng Chen, M. Mojarradi, E. Kolawa","doi":"10.1109/UGIM.2003.1225711","DOIUrl":"https://doi.org/10.1109/UGIM.2003.1225711","url":null,"abstract":"The INSYTE (Integrated Circuits and Systems) Laboratory at The University of Tennessee is currently investigating robust CMOS analog and mixed-signal circuit design techniques for extreme environments. This work is being targeted for Mars surface applications where the temperature can vary from -1200/spl square/C to +20/spl square/C depending on time of day and location. In this paper we present both robust analog design techniques and measurement results from several test circuits. The design techniques focus on developing high performance OTAs and op-amps that can operate over a wide temperature range. The test circuits include a 3.3 V ping-pong op-amp and a 3.3 V rail-to-rail I/O op-amp capable of driving resistive loads.","PeriodicalId":356452,"journal":{"name":"Proceedings of the 15th Biennial University/Government/ Industry Microelectronics Symposium (Cat. No.03CH37488)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134149557","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Quest for the ultimate sub-50 nm CMOS transistor structure","authors":"A. Rambhatla, D. Hackler, S. Parke","doi":"10.1109/UGIM.2003.1225730","DOIUrl":"https://doi.org/10.1109/UGIM.2003.1225730","url":null,"abstract":"In this paper, we seek to comparatively investigate CMOS transistor structure from first-principles in the quest to find the ultimate transistor structure that will permit evolutionary improvement of the existing worldwide CMOS technology base, complementing the inevitable revolutionary CMOS replacement technologies.","PeriodicalId":356452,"journal":{"name":"Proceedings of the 15th Biennial University/Government/ Industry Microelectronics Symposium (Cat. No.03CH37488)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132850611","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}