Proceedings of the 15th Biennial University/Government/ Industry Microelectronics Symposium (Cat. No.03CH37488)最新文献_第2页

Flip-chip-in-a-package solder joint reliability simulation 倒装片封装焊点可靠性仿真

Proceedings of the 15th Biennial University/Government/ Industry Microelectronics Symposium (Cat. No.03CH37488) Pub Date : 2003-09-04 DOI: 10.1109/UGIM.2003.1225734

S. Groothuis, T. Jiang, Yong Du

引用次数: 0

Laboratory facilities of the microsystems technology laboratories (MTL) at Massachusetts Institute of Technology 麻省理工学院微系统技术实验室(MTL)的实验室设施

Proceedings of the 15th Biennial University/Government/ Industry Microelectronics Symposium (Cat. No.03CH37488) Pub Date : 2003-09-04 DOI: 10.1109/UGIM.2003.1225691

V. Diadiuk

引用次数: 0

A benzene selective electrode

Proceedings of the 15th Biennial University/Government/ Industry Microelectronics Symposium (Cat. No.03CH37488) Pub Date : 2003-09-04 DOI: 10.1109/UGIM.2003.1225763

L. Warner, D. Russell, J. Scaggs

引用次数: 0

Optimization of Bosch etch process for through wafer interconnects 通过晶圆互连的博世蚀刻工艺优化

Proceedings of the 15th Biennial University/Government/ Industry Microelectronics Symposium (Cat. No.03CH37488) Pub Date : 2003-09-04 DOI: 10.1109/UGIM.2003.1225759

L. Kenoyer, R. Oxford, A. Moll

引用次数: 12

Characterization of the effect of TiN oxidation on via resistance TiN氧化对通孔电阻影响的表征

Proceedings of the 15th Biennial University/Government/ Industry Microelectronics Symposium (Cat. No.03CH37488) Pub Date : 2003-09-04 DOI: 10.1109/UGIM.2003.1225695

K. Gunturu, T. Haskett, T. Corsetti, M. Engle, J. Prasad

引用次数: 0

Enhanced hot-carrier induced degradation in pMOSFETs stressed under high gate voltage 高栅极电压下pmosfet的热载流子诱导退化

Proceedings of the 15th Biennial University/Government/ Industry Microelectronics Symposium (Cat. No.03CH37488) Pub Date : 2003-09-04 DOI: 10.1109/UGIM.2003.1225732

J.F. Chen, C. Tsao, T. Ong

引用次数: 0

Low-latency multiple clock domain interfacing without alteration of local clocks 低延迟多时钟域接口，不改变本地时钟

Proceedings of the 15th Biennial University/Government/ Industry Microelectronics Symposium (Cat. No.03CH37488) Pub Date : 2003-09-04 DOI: 10.1109/UGIM.2003.1225761

S.F. Smith, J. Frenzel

引用次数: 6

Teaching vacuum technology using spreadsheet calculations 使用电子表格计算教学真空技术

Proceedings of the 15th Biennial University/Government/ Industry Microelectronics Symposium (Cat. No.03CH37488) Pub Date : 2003-09-04 DOI: 10.1109/UGIM.2003.1225757

R. E. Pearson, G. Atkinson

引用次数: 2

Neural network modeling of the resistance of metallized vias formed by laser ablation in polymer dielectrics 聚合物电介质中激光烧蚀形成金属化过孔电阻的神经网络建模

Proceedings of the 15th Biennial University/Government/ Industry Microelectronics Symposium (Cat. No.03CH37488) Pub Date : 2003-09-04 DOI: 10.1109/UGIM.2003.1225733

R. Setia, G. May

{"title":"Neural network modeling of the resistance of metallized vias formed by laser ablation in polymer dielectrics","authors":"R. Setia, G. May","doi":"10.1109/UGIM.2003.1225733","DOIUrl":"https://doi.org/10.1109/UGIM.2003.1225733","url":null,"abstract":"Laser ablation, a material removal process that uses localized thermal energy caused by stimulated radiation, has become an important process in the fabrication of microelectronic packaging substrates, particularly in the fabrication of vias. During laser ablation, debris in the form of carbon residue is generated as a by-product. In this paper, resistance measurements on metal deposited in ablated vias are conducted to characterize the degree to which debris remaining inside the vias affects their quality. Vias with diameters of 10-50 /spl mu/m are ablated in DuPont Kapton/spl reg/ E polyimide using an Anvik HexScan/spl trade/ 2150 SXE excimer laser. A statistical experiment using a 2/sup 5-1/ fractional factorial design is conducted to characterize five process conditions, namely: laser energy, shot frequency, number of pulses, and the vertical and horizontal positions of the debris removal system in the laser tool. Measurements indicate that 10, 20, and 30 /spl mu/m vias are not opened by any combination of the five process conditions. As for the 40 and 50 /spl mu/m vias, both number of pulses and the horizontal position of the debris removal system, as well as their two-term interaction, are found to be statistically significant (p-value<0.05). Following the collection of the experimental data, neural networks are trained and subsequently tested to model the measured resistance through the metallized 40 and 50 /spl mu/m vias. Results indicate that the prediction error of these models is less than 15%.","PeriodicalId":356452,"journal":{"name":"Proceedings of the 15th Biennial University/Government/ Industry Microelectronics Symposium (Cat. No.03CH37488)","volume":"431 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133819298","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

Gate dielectric degradation effects on nMOS devices using a noise model approach 栅极介电退化对nMOS器件的影响

Proceedings of the 15th Biennial University/Government/ Industry Microelectronics Symposium (Cat. No.03CH37488) Pub Date : 2003-09-04 DOI: 10.1109/UGIM.2003.1225739

C. Lawrence, B. Cheek, T.E. Lawrence, S. Kumar, A. Haggag, R. J. Baker, W. B. Knowlton

引用次数: 1