低延迟多时钟域接口，不改变本地时钟

Proceedings of the 15th Biennial University/Government/ Industry Microelectronics Symposium (Cat. No.03CH37488) Pub Date : 2003-09-04 DOI:10.1109/UGIM.2003.1225761

S.F. Smith, J. Frenzel

{"title":"低延迟多时钟域接口，不改变本地时钟","authors":"S.F. Smith, J. Frenzel","doi":"10.1109/UGIM.2003.1225761","DOIUrl":null,"url":null,"abstract":"A method for interfacing synchronous blocks of logic with different local clocks is presented which introduces very little latency and avoids metastability. The method does not require stopping or stretching local clocks and enforces correct operation of a bundled data constraint for all but very wide data paths.","PeriodicalId":356452,"journal":{"name":"Proceedings of the 15th Biennial University/Government/ Industry Microelectronics Symposium (Cat. No.03CH37488)","volume":"324 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2003-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"6","resultStr":"{\"title\":\"Low-latency multiple clock domain interfacing without alteration of local clocks\",\"authors\":\"S.F. Smith, J. Frenzel\",\"doi\":\"10.1109/UGIM.2003.1225761\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A method for interfacing synchronous blocks of logic with different local clocks is presented which introduces very little latency and avoids metastability. The method does not require stopping or stretching local clocks and enforces correct operation of a bundled data constraint for all but very wide data paths.\",\"PeriodicalId\":356452,\"journal\":{\"name\":\"Proceedings of the 15th Biennial University/Government/ Industry Microelectronics Symposium (Cat. No.03CH37488)\",\"volume\":\"324 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2003-09-04\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"6\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of the 15th Biennial University/Government/ Industry Microelectronics Symposium (Cat. No.03CH37488)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/UGIM.2003.1225761\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the 15th Biennial University/Government/ Industry Microelectronics Symposium (Cat. No.03CH37488)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/UGIM.2003.1225761","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 6

摘要

提出了一种同步逻辑块与不同本地时钟接口的方法，该方法引入了很小的延迟并避免了亚稳态。该方法不需要停止或扩展本地时钟，并且除了非常宽的数据路径外，还强制对所有绑定的数据约束进行正确操作。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

查看原文本刊更多论文

Low-latency multiple clock domain interfacing without alteration of local clocks

A method for interfacing synchronous blocks of logic with different local clocks is presented which introduces very little latency and avoids metastability. The method does not require stopping or stretching local clocks and enforces correct operation of a bundled data constraint for all but very wide data paths.

求助全文

通过发布文献求助，成功后即可免费获取论文全文。去求助

来源期刊

Proceedings of the 15th Biennial University/Government/ Industry Microelectronics Symposium (Cat. No.03CH37488)

自引率

0.00%

发文量