Optimization of Bosch etch process for through wafer interconnects

L. Kenoyer, R. Oxford, A. Moll
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引用次数: 12

Abstract

The Bosch etch process was utilized to create 50 micrometer vias with an aspect ration of 10:1 in silicon wafers for through wafer interconnects. The process is complex with twenty-two separate parameters required to control the process. Deviating from the standard process and flowing SF/sub 6/ during the deposition process resulted in a more stable and reproducible process.
通过晶圆互连的博世蚀刻工艺优化
博世蚀刻工艺用于在硅片上创建50微米的通孔,其纵横比为10:1,用于通过晶圆互连。这个过程很复杂,需要22个独立的参数来控制这个过程。在沉积过程中,偏离标准工艺,流动SF/sub / 6,使过程更加稳定,重现性更好。
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