Proceedings of the 15th Biennial University/Government/ Industry Microelectronics Symposium (Cat. No.03CH37488)最新文献

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High voltage bandgap reference design using SOI technology 基于SOI技术的高压带隙参考设计
V. Sukumar, S. Subramanium, D. Pan, K. Buck, H. Hess, H.W. Li, D. Cox, M. Mojarradi
{"title":"High voltage bandgap reference design using SOI technology","authors":"V. Sukumar, S. Subramanium, D. Pan, K. Buck, H. Hess, H.W. Li, D. Cox, M. Mojarradi","doi":"10.1109/UGIM.2003.1225710","DOIUrl":"https://doi.org/10.1109/UGIM.2003.1225710","url":null,"abstract":"A high voltage bandgap reference circuit has been designed and implemented in an SOI CMOS technology. The design is capable of maintaining a stable value, in the temperature range from 0/spl deg/C to 100/spl deg/C. The design is also validated against process and power supply fluctuations. An innovative approach replaces the traditional lateral pnp transistor method.","PeriodicalId":356452,"journal":{"name":"Proceedings of the 15th Biennial University/Government/ Industry Microelectronics Symposium (Cat. No.03CH37488)","volume":"86 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121206456","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Integration of BaTiO/sub 3/ferroelectric thin films with GaAs for functional devices BaTiO/sub - 3/铁电薄膜与功能器件GaAs的集成
T. E. Murphy, Ding-Yuan Chen, J. Phillips
{"title":"Integration of BaTiO/sub 3/ferroelectric thin films with GaAs for functional devices","authors":"T. E. Murphy, Ding-Yuan Chen, J. Phillips","doi":"10.1109/UGIM.2003.1225740","DOIUrl":"https://doi.org/10.1109/UGIM.2003.1225740","url":null,"abstract":"The integration of ferroelectric oxides with GaAs could enable monolithic optoelectronic integrated circuits, advanced metal-insulator-semiconductor structures, and multifunctional optoelectronic devices. BaTiO/sub 3/ is a good candidate for this integration due to the large spontaneous polarization and large electro-optic effects, but presents a challenge due to the large lattice mismatch and difficulty in achieving a crystalline oxide interface on GaAs. In this paper we investigate the deposition of BaTiO/sub 3/ onto GaAs by pulsed laser deposition using varied substrate preparation techniques and MgO buffer layers. Highly oriented [001] BaTiO/sub 3/ thin films are achieved exhibiting spontaneous polarization characteristic of ferroelectric material.","PeriodicalId":356452,"journal":{"name":"Proceedings of the 15th Biennial University/Government/ Industry Microelectronics Symposium (Cat. No.03CH37488)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117188854","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Bulk micromachined pressure sensor 散装微机械压力传感器
L. Fuller, S. Sudirgo
{"title":"Bulk micromachined pressure sensor","authors":"L. Fuller, S. Sudirgo","doi":"10.1109/UGIM.2003.1225752","DOIUrl":"https://doi.org/10.1109/UGIM.2003.1225752","url":null,"abstract":"Bulk micromachined piezoresistive pressure sensor was designed, fabricated, packaged, and tested at RIT laboratory facility. Every aspect of the fabrication is studied thoroughly and used as an educational tool in better understanding the fabrication of MEMs devices.","PeriodicalId":356452,"journal":{"name":"Proceedings of the 15th Biennial University/Government/ Industry Microelectronics Symposium (Cat. No.03CH37488)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116179698","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 22
Bridging the gap between classical and quantum transport in nanoscale MOSFETs: Schrodinger equation Monte Carlo-2D 纳米级mosfet中经典输运与量子输运之间的桥梁:薛定谔方程Monte Carlo-2D
L. Register, W. Chen, S. Banerjee
{"title":"Bridging the gap between classical and quantum transport in nanoscale MOSFETs: Schrodinger equation Monte Carlo-2D","authors":"L. Register, W. Chen, S. Banerjee","doi":"10.1109/UGIM.2003.1225724","DOIUrl":"https://doi.org/10.1109/UGIM.2003.1225724","url":null,"abstract":"As MOSFET channel lengths approach the nanoscale, the reliability of semi-classical models of transport decreases. However, we have not yet, nor perhaps ever will we, reach the point where effects related to scattering such as mobility degradation and electrostatic screening can be neglected. To offer additional insight into transport phenomena in these deeply scaled devices, simulation tools that treat quantum transport without sacrificing the realistic treatment of scattering are needed. In recent years we and colleagues have been developing a unique non-equilibrium Green's function approach \"Schrodinger Equation Monte Carlo\" (SEMC) that provides a physically rigorous approach to quantum transport and phase-breaking inelastic scattering via real (actual) scattering processes such as optical and acoustic phonon scattering. Quasi-one-dimensional SEMC codes previously have been applied to model transport in systems such as quantum well lasers where the potential varies only along the nominal direction of transport, although with a fully three-dimensional (3D) treatment of scattering. In this paper, the development of a \"SEMC-2D\" code for electrostatically self-consistent treatment of quantum transport within devices with, additionally, quantum confinement normal to the direction of transport, is reported along with illustrative simulation results for nano-scaled SOI MOSFETs geometries.","PeriodicalId":356452,"journal":{"name":"Proceedings of the 15th Biennial University/Government/ Industry Microelectronics Symposium (Cat. No.03CH37488)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121837614","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Determination and optimization of film adhesive cure in board-on-chip packaged semiconductors 片上封装半导体薄膜胶粘剂固化性能的测定与优化
J. Rumps, C. Bradbury, B. Fosbinder
{"title":"Determination and optimization of film adhesive cure in board-on-chip packaged semiconductors","authors":"J. Rumps, C. Bradbury, B. Fosbinder","doi":"10.1109/UGIM.2003.1225735","DOIUrl":"https://doi.org/10.1109/UGIM.2003.1225735","url":null,"abstract":"Summary form only given. Adequate die-to-substrate adhesion is essential to ensure board-on-chip (BOC) package integrity during and after the manufacturing process. Inadequate adhesion can result in a variety of defects, such as die adhesion failure, marginal wire bond, broken wire and bent leads, and ultimately lead to electrical failure. The BOC die attach method of laminations using film adhesives provides ease of application and consistent bond line thickness. Processing problems due to inconsistency of film adhesive manufacture, however, can occur. Differential scanning calorimetry (DSC), contact angle, and hardness were used to determine the consistency of blended-polymer b-staged thermosets. These analytical techniques were shown to be useful incoming inspection monitors or preapplied film adhesives and provided a means of eliminating inadequate adhesion at die attach.","PeriodicalId":356452,"journal":{"name":"Proceedings of the 15th Biennial University/Government/ Industry Microelectronics Symposium (Cat. No.03CH37488)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122197897","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Mixed-signal design in the microelectronics curriculum 微电子课程中的混合信号设计
R. J. Baker
{"title":"Mixed-signal design in the microelectronics curriculum","authors":"R. J. Baker","doi":"10.1109/UGIM.2003.1225698","DOIUrl":"https://doi.org/10.1109/UGIM.2003.1225698","url":null,"abstract":"This paper discusses educating electrical engineering students so they can do mixed-signal design (MSD). It also discusses why MSD is important and how it fits into a contemporary electrical engineering curriculum. The paper concludes with a practical example of MSD (the design of a memory sensing circuit) that shows the benefits over traditional analog techniques.","PeriodicalId":356452,"journal":{"name":"Proceedings of the 15th Biennial University/Government/ Industry Microelectronics Symposium (Cat. No.03CH37488)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123320195","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Challenges in integration of Resonant Interband Tunnel Devices with CMOS 共振带间隧道器件与CMOS集成的挑战
S. Sudirgo, B. Curanovic, S. Rommel, K. Hirschman, S. Kurinec, Niu Jin, A. T. Rice, Paul R. Berger, P. Thompson
{"title":"Challenges in integration of Resonant Interband Tunnel Devices with CMOS","authors":"S. Sudirgo, B. Curanovic, S. Rommel, K. Hirschman, S. Kurinec, Niu Jin, A. T. Rice, Paul R. Berger, P. Thompson","doi":"10.1109/UGIM.2003.1225742","DOIUrl":"https://doi.org/10.1109/UGIM.2003.1225742","url":null,"abstract":"The fabrication of SiGe Resonant Interband Tunnel Devices (RITD) using CMOS compatible processes requires ability to form RITD structures selectively on source/drain regions. Various approaches were investigated and RITDs have been realized in lithographically defined openings in oxide on Si wafers. Patterned growth RITD on p+ Si exhibited a peak-to-valley current ratio (PVCR) of 3.0 and peak current density (J/sub p/) of 188 A/cm/sup 2/ whereas RITD on p+ implanted regions resulted in a PVCR of 2.5 with J/sub p/ of 278 A/cm/sup 2/. Blanket growth RITD on p+ implanted substrate yielded a superior PCVR of 3.3 and J/sub p/ of 332 A/cm/sup 2/. The observed effects of patterned growth and implanted substrate on the RITD device performance are critical challenges addressed in this study for RITD-CMOS integration.","PeriodicalId":356452,"journal":{"name":"Proceedings of the 15th Biennial University/Government/ Industry Microelectronics Symposium (Cat. No.03CH37488)","volume":"91 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131860419","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Temperature fluctuations and 1/f noise in electron devices 电子器件中的温度波动和1/f噪声
L. Forbes, X.Y. Wang, C.W. Zhang
{"title":"Temperature fluctuations and 1/f noise in electron devices","authors":"L. Forbes, X.Y. Wang, C.W. Zhang","doi":"10.1109/UGIM.2003.1225764","DOIUrl":"https://doi.org/10.1109/UGIM.2003.1225764","url":null,"abstract":"Hooge's empirical equation for the 1/f noise of resistors has been shown to be described by temperature fluctuations and Hooge's parameter was shown to be simply related to the ratio of the total number of conduction electrons and total number of atoms in the sample. At low frequencies the mean square temperature fluctuation around the average temperature depends on the diffusion transit time to the heat sink and inversely on the number of atoms in the sample. At higher frequencies temperature fluctuations are attenuated by the heat capacity of the sample which results in the 1/f frequency dependence of temperature fluctuations. Here the results for these temperature fluctuations are applied to describe the 1/f noise of bipolar transistors. In bipolar transistors the current is an exponential function of temperature so the noise is easier to observe and measure.","PeriodicalId":356452,"journal":{"name":"Proceedings of the 15th Biennial University/Government/ Industry Microelectronics Symposium (Cat. No.03CH37488)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128510370","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Theoretical and experimental study of fluid behavior of a peristaltic micropump 蠕动微泵流体特性的理论与实验研究
S. Na, S. Ridgeway, Li Cao
{"title":"Theoretical and experimental study of fluid behavior of a peristaltic micropump","authors":"S. Na, S. Ridgeway, Li Cao","doi":"10.1109/UGIM.2003.1225751","DOIUrl":"https://doi.org/10.1109/UGIM.2003.1225751","url":null,"abstract":"An embedded PZT actuated peristaltic micropump that is a part of an implantable medical drug delivery system was designed and fabricated using Microelectromechanical Systems (MEMS) technology. Three embedded PZT actuators drive the three micropump chambers in a peristaltic motion. Static deflection data of the micropump chamber actuated by the PZT was measured using Atomic Force Microscope (AFM). The deflection data are linear below 90 volts and initiate a slightly non-linear behavior above 90 volts to 130 volts that is the maximum voltage we drive our micropump. In order to obtain linear response between driving voltage and pumping performance, it is recommended to drive the embedded PZT to actuate the peristaltic micropump below 90 volts. Volumetric flow rate and maximum pumping pressure data of the peristaltic micropump for four different driving frequencies (0.5 Hz, 1 Hz, 2 Hz, and 4 Hz) at 90 volts were tested. Volumetric flow rate and maximum pumping pressure data of the peristaltic micropump for four different driving frequencies (0.5 Hz, 1 Hz, 2 Hz, and 4 Hz) at 130 volts were tested. The overall efficiency of the micropump for two driving voltages (90 volts and 130 volts) was calculated. For a volumetric flowrate of 6 /spl mu/L/min, the overall efficiency for the micropump driven at 90 volts was achieved at 0.015%. If our desired volumetric flowrate of the micropump is 10 /spl mu/L/min, the overall efficiency for the micropump driven at 90 volts will be even lower. This low overall efficiency tendency for the micropump is due to the more input power to increase the pumping performance. For the same volumetric flowrate of 6 /spl mu/L/min, the overall efficiency for the micropump driven at 130 volts was achieved at 0.060%, which is four times of the overall efficiency for the micropump driven at 90 volts. To improve the overall efficiency for the micropump that is for implanted) medical drug delivery systems, we recommend driving the micropump at a higher voltage than 90 volts. A theoretical model of the fluid behavior of the micropump was also developed with the assumption that the peristaltic micropump is working in a steady state flow. The fluid static behaviors (deflection, flowrate, and pumping pressure) from this model were compared with our experiment data. The experimental data meet with our theoretical model well.","PeriodicalId":356452,"journal":{"name":"Proceedings of the 15th Biennial University/Government/ Industry Microelectronics Symposium (Cat. No.03CH37488)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132391902","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
Challenges and opportunities for the universities to support future technology developments in the semiconductor industry: staying on the Moore's Law 大学支持半导体行业未来技术发展的挑战和机遇:遵循摩尔定律
J. Prasad
{"title":"Challenges and opportunities for the universities to support future technology developments in the semiconductor industry: staying on the Moore's Law","authors":"J. Prasad","doi":"10.1109/UGIM.2003.1225719","DOIUrl":"https://doi.org/10.1109/UGIM.2003.1225719","url":null,"abstract":"Moore's 1/sup st/ law requires performance scaling and thus the improved transistor I/sub dsat/. To improve transistor I/sub dsat/ one need to increase the channel mobility and reduce the oxide thickness. Improvement in channel mobility requires channel and interface engineering. The reduction in SiO/sub 2/ thickness has limits due to undesired effects on the leakage current. This limit on the SiO/sub 2/ thickness has already been reached for current generation devices and therefore new dielectric materials with high k are needed to minimize the leakage. Industry has not yet decided on the material due to integration process problems and has delayed the introduction of low standby power (LSTP) devices. Thus it's important to decide the next generation dielectric materials and solve the associated integration problems quickly to stay on the productivity curve and, thus, Moore's Law. In the past 10 years, the growing size of required investments has motivated industry collaboration with the research universities and the trend is accelerating. There are huge opportunities for the research organizations to contribute and help the semiconductor industry to stay on pace with Moore's Law. The thrust of this paper will be to review the current status of the front-end issues and identify the areas for future research.","PeriodicalId":356452,"journal":{"name":"Proceedings of the 15th Biennial University/Government/ Industry Microelectronics Symposium (Cat. No.03CH37488)","volume":"96 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133143354","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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