共振带间隧道器件与CMOS集成的挑战

Proceedings of the 15th Biennial University/Government/ Industry Microelectronics Symposium (Cat. No.03CH37488) Pub Date : 2003-09-04 DOI:10.1109/UGIM.2003.1225742

S. Sudirgo, B. Curanovic, S. Rommel, K. Hirschman, S. Kurinec, Niu Jin, A. T. Rice, Paul R. Berger, P. Thompson

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引用次数: 5

摘要

使用CMOS兼容工艺制造SiGe谐振带间隧道器件(RITD)需要能够在源/漏区选择性地形成RITD结构。研究了各种方法，并在硅晶片上的氧化物上通过光刻定义的开口实现了ritd。在p+ Si上生长的RITD的峰谷电流比(PVCR)为3.0，峰值电流密度(J/sub p/)为188 a /cm/sup 2/，而在p+植入区域上生长的RITD的PVCR为2.5,J/sub p/为278 a /cm/sup 2/。在p+注入的底物上，毯状生长RITD的PCVR为3.3,J/sub p/为332 a /cm/sup 2/。观察到的图案生长和植入衬底对RITD器件性能的影响是本研究中RITD- cmos集成的关键挑战。

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Challenges in integration of Resonant Interband Tunnel Devices with CMOS

The fabrication of SiGe Resonant Interband Tunnel Devices (RITD) using CMOS compatible processes requires ability to form RITD structures selectively on source/drain regions. Various approaches were investigated and RITDs have been realized in lithographically defined openings in oxide on Si wafers. Patterned growth RITD on p+ Si exhibited a peak-to-valley current ratio (PVCR) of 3.0 and peak current density (J/sub p/) of 188 A/cm/sup 2/ whereas RITD on p+ implanted regions resulted in a PVCR of 2.5 with J/sub p/ of 278 A/cm/sup 2/. Blanket growth RITD on p+ implanted substrate yielded a superior PCVR of 3.3 and J/sub p/ of 332 A/cm/sup 2/. The observed effects of patterned growth and implanted substrate on the RITD device performance are critical challenges addressed in this study for RITD-CMOS integration.

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Proceedings of the 15th Biennial University/Government/ Industry Microelectronics Symposium (Cat. No.03CH37488)

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