Challenges and opportunities for the universities to support future technology developments in the semiconductor industry: staying on the Moore's Law

Moore's 1/sup st/ law requires performance scaling and thus the improved transistor I/sub dsat/. To improve transistor I/sub dsat/ one need to increase the channel mobility and reduce the oxide thickness. Improvement in channel mobility requires channel and interface engineering. The reduction in SiO/sub 2/ thickness has limits due to undesired effects on the leakage current. This limit on the SiO/sub 2/ thickness has already been reached for current generation devices and therefore new dielectric materials with high k are needed to minimize the leakage. Industry has not yet decided on the material due to integration process problems and has delayed the introduction of low standby power (LSTP) devices. Thus it's important to decide the next generation dielectric materials and solve the associated integration problems quickly to stay on the productivity curve and, thus, Moore's Law. In the past 10 years, the growing size of required investments has motivated industry collaboration with the research universities and the trend is accelerating. There are huge opportunities for the research organizations to contribute and help the semiconductor industry to stay on pace with Moore's Law. The thrust of this paper will be to review the current status of the front-end issues and identify the areas for future research.