采用隧道外延和氮化栅极氧化物的计划6.3 nm薄体SOI MOSFET

Proceedings of the 15th Biennial University/Government/ Industry Microelectronics Symposium (Cat. No.03CH37488) Pub Date : 2003-09-04 DOI:10.1109/UGIM.2003.1225743

S.S. Ahmed, G. Neudeck, J. Denton, M. Stidham

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引用次数: 0

摘要

采用隧道外延技术制备了一种单门UTB SOI MOSFET，形成了厚度为6.3 nm的硅沟道。对多种器件进行了实验电测量，并对实验结果进行了总结。测量了低漏电流，其中栅极漏15 pA，器件漏1.1 pA。测量的I/spl平方/V特性还包括67 mV/dec的亚阈值斜率。， DIBL为10mv /V，驱动电流高达280/spl平方/A。

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A planner 6.3 nm thin-body SOI MOSFET using tunnel epitaxy and nitrided gate oxides

A single-gate UTB SOI MOSFET was fabricated using tunnel epitaxy to form the silicon channel as thin as 6.3 nm. Experimental electrical measurements were conducted on a variety of devices, and the results are summarized. Low leakage currents were measured including gate leakage of 15 pA and device leakage of 1.1 pA. Measured I/spl square/V characteristics also included subthreshold slopes of 67 mV/dec., DIBL of 10 mV/V, and drive currents up to 280/spl square/A.

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Proceedings of the 15th Biennial University/Government/ Industry Microelectronics Symposium (Cat. No.03CH37488)

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