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2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)最新文献

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Experimental Demonstration of An Inversion-Type Ferroelectric Capacitive Memory and its 1 kbit Crossbar Array Featuring High CHCS/CLCS, Fast Speed, and Long Retention 一种高CHCS/CLCS、速度快、保持时间长的反转型铁电电容存储器及其1kbit交叉棒阵列的实验演示
2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) Pub Date : 2022-06-12 DOI: 10.1109/vlsitechnologyandcir46769.2022.9830291
Zuopu Zhou, Jiao Leming, Jiuren Zhou, Zijie Zheng, Yue Chen, Kaizhen Han, Yuye Kang, Xiao-Qing Gong
{"title":"Experimental Demonstration of An Inversion-Type Ferroelectric Capacitive Memory and its 1 kbit Crossbar Array Featuring High CHCS/CLCS, Fast Speed, and Long Retention","authors":"Zuopu Zhou, Jiao Leming, Jiuren Zhou, Zijie Zheng, Yue Chen, Kaizhen Han, Yuye Kang, Xiao-Qing Gong","doi":"10.1109/vlsitechnologyandcir46769.2022.9830291","DOIUrl":"https://doi.org/10.1109/vlsitechnologyandcir46769.2022.9830291","url":null,"abstract":"By introducing a heavily doped region in the metal-ferroelectric-semiconductor (MFS) structure, for the first time, we report an inversion-type ferroelectric capacitive memory (FCM) device which simultaneously achieves (1) high (×125) CHCS/CLCS ratio, (2) 10-year retention under 85 ℃, (3) multi-state operation, and (4) improved write speed in nanosecond range. Integrating the devices on SOI substrates, we also realize the world’s first 1 kbit inversion-type FCM crossbar array and demonstrate successful read/write operation with a specially-designed array drive and test system.","PeriodicalId":332454,"journal":{"name":"2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133962288","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
A Magnetically Coupled Dual-Core 154-GHz Class-F Oscillator with -177.1 FoM and -87 dBc/Hz PN at 1-MHz Offset in a 22-nm FDSOI with Third-Harmonic Extraction 一种磁耦合双核154-GHz f类振荡器，在1 mhz偏置下具有-177.1 FoM和-87 dBc/Hz PN，采用22nm FDSOI进行三次谐波提取
2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) Pub Date : 2022-06-12 DOI: 10.1109/vlsitechnologyandcir46769.2022.9830187
Sarthak Sharma, Hao Gao, G. Hueber, A. Mazzanti
{"title":"A Magnetically Coupled Dual-Core 154-GHz Class-F Oscillator with -177.1 FoM and -87 dBc/Hz PN at 1-MHz Offset in a 22-nm FDSOI with Third-Harmonic Extraction","authors":"Sarthak Sharma, Hao Gao, G. Hueber, A. Mazzanti","doi":"10.1109/vlsitechnologyandcir46769.2022.9830187","DOIUrl":"https://doi.org/10.1109/vlsitechnologyandcir46769.2022.9830187","url":null,"abstract":"This paper presents a 142-154 GHz third-harmonic extracted Class-F oscillator featuring an FoM of -177.1 at 1-MHz offset. In this work, a magnetically coupled dual-core topology is applied to enhance the third harmonic for Class-F operation, which also effectively boosts the negative conductance of the oscillator. The boosted negative conductance relaxes the startup condition in the Colpitts oscillator and improves its phase noise. This oscillator is fabricated in a 22-nm CMOS FDSOI. At 154.5 GHz, the measured PN is -87.4 dBc/Hz at 1-MHz offset, and -101.8 dBc/Hz at 10 MHz offset.","PeriodicalId":332454,"journal":{"name":"2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128760812","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
SoIC_H Technology for Heterogenous System Integration 异构系统集成的SoIC_H技术
2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) Pub Date : 2022-06-12 DOI: 10.1109/vlsitechnologyandcir46769.2022.9830182
Chuei-Tang Wang, Chia-Chia Lin, Chih-Hsin Lu, Wei-Ting Chen, C. Tsai, Douglas C. H. Yu
{"title":"SoIC_H Technology for Heterogenous System Integration","authors":"Chuei-Tang Wang, Chia-Chia Lin, Chih-Hsin Lu, Wei-Ting Chen, C. Tsai, Douglas C. H. Yu","doi":"10.1109/vlsitechnologyandcir46769.2022.9830182","DOIUrl":"https://doi.org/10.1109/vlsitechnologyandcir46769.2022.9830182","url":null,"abstract":"An SoIC_H technology for 2.5D heterogeneous system integration is proposed. SoIC bond, replacing µbump, is used to provide low parasitic and high density of interconnects. Through system technology co-optimization (STCO), the proposed architecture provides over 60% power reduction for die-to-die I/O link and 81%, 14%, and 94% reductions in energy, latency, and area, respectively, for on-chip fanout design. For memory cubes, it introduces 61% latency and 49% energy reductions for 4-Hi SRAM cache and 30% bandwidth and 28% energy efficiency improvements for 12-Hi HBM.","PeriodicalId":332454,"journal":{"name":"2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129049176","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
1200x84-pixels 30fps 64cc Solid-State LiDAR RX with an HV/LV transistors Hybrid Active-Quenching-SPAD Array and Background Digital PT Compensation 1200x84像素30fps 64cc固态激光雷达RX与高压/低压晶体管混合有源淬火- spad阵列和背景数字PT补偿
2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) Pub Date : 2022-06-12 DOI: 10.1109/vlsitechnologyandcir46769.2022.9830414
Toshiki Sugimoto, T. Ta, K. Kokubun, Satoshi Kondo, T. Itakura, Hisaaki Katagiri, Yutaka Ota, M. Sengoku, H. Kwon, K. Sasaki, H. Kubota, Kazuhiro Suzuki, K. Kimura, A. Sai
{"title":"1200x84-pixels 30fps 64cc Solid-State LiDAR RX with an HV/LV transistors Hybrid Active-Quenching-SPAD Array and Background Digital PT Compensation","authors":"Toshiki Sugimoto, T. Ta, K. Kokubun, Satoshi Kondo, T. Itakura, Hisaaki Katagiri, Yutaka Ota, M. Sengoku, H. Kwon, K. Sasaki, H. Kubota, Kazuhiro Suzuki, K. Kimura, A. Sai","doi":"10.1109/vlsitechnologyandcir46769.2022.9830414","DOIUrl":"https://doi.org/10.1109/vlsitechnologyandcir46769.2022.9830414","url":null,"abstract":"This paper presents two essential techniques, Active-Quenching (AQ) -SPAD consisting of hybrid HV/LV transistors and Digital SPAD Characteristic Compensation (DSCC) circuit to realize high-performance and palm-size LiDAR. The hybrid AQ circuit shrinks a pixel area while ensures a high PDE. The high pixel density 2D-SPAD array realizes high image-resolution palm-size LiDAR by reducing light-receiving lens and RX unit size. The DSCC provides an on-chip Process/Temperature (PT) calibration without external components, which contributes to weatherability assurance and LiDAR miniaturization. These technologies downsize LiDAR RX to the world’s smallest size, 64cc, and realize a total 350cc-size LiDAR with the competitive performance as a mechanical one.","PeriodicalId":332454,"journal":{"name":"2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129128125","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 72GS/s, 8-bit DAC-based Wireline Transmitter in 4nm FinFET CMOS for 200+Gb/s Serial Links 72GS/s, 8位基于dac的有线发射机，4nm FinFET CMOS，用于200+Gb/s串行链路
2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) Pub Date : 2022-06-12 DOI: 10.1109/vlsitechnologyandcir46769.2022.9830421
T. Dickson, Z. Deniz, M. Cochet, M. Kossel, T. Morf, Young-Ho Choi, P. Francese, M. Brändli, T. Beukema, C. Baks, J. Proesel, J. Bulzacchelli, Michael P. Beakes, Byoung-Joo Yoo, Hyoungbae Ahn, Dong-Hyuk Lim, Gunil Kang, Sang-Hune Park, M. Meghelli, Hyo-Gyuem Rhew, D. Friedman, Michael Choi, M. Soyuer, Jongshin Shin
{"title":"A 72GS/s, 8-bit DAC-based Wireline Transmitter in 4nm FinFET CMOS for 200+Gb/s Serial Links","authors":"T. Dickson, Z. Deniz, M. Cochet, M. Kossel, T. Morf, Young-Ho Choi, P. Francese, M. Brändli, T. Beukema, C. Baks, J. Proesel, J. Bulzacchelli, Michael P. Beakes, Byoung-Joo Yoo, Hyoungbae Ahn, Dong-Hyuk Lim, Gunil Kang, Sang-Hune Park, M. Meghelli, Hyo-Gyuem Rhew, D. Friedman, Michael Choi, M. Soyuer, Jongshin Shin","doi":"10.1109/vlsitechnologyandcir46769.2022.9830421","DOIUrl":"https://doi.org/10.1109/vlsitechnologyandcir46769.2022.9830421","url":null,"abstract":"A DAC-based SST transmitter for wireline applications is reported in a 4nm FinFET technology. 8b resolution and high analog output bandwidth (BW) are achieved by employing a segmented architecture along with a single-ended LSB. Hybrid analog/digital tuning is used in the DAC LSB segments, resulting in well-matched MSB/LSB segments with -0.63/0.67 LSB INL and -0.16/0.43 LSB DNL. 216Gb/s PAM8 and 212Gb/s QAM64 OFDM operation are demonstrated at 288mW from a 0.95V supply.","PeriodicalId":332454,"journal":{"name":"2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129170787","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Gain-Cell CIM: Leakage and Bitline Swing Aware 2T1C Gain-Cell eDRAM Compute in Memory Design with Bitline Precharge DACs and Compact Schmitt Trigger ADCs 增益单元CIM:泄漏和位线摆动感知的2T1C增益单元eDRAM内存设计与位线预充dac和紧凑型施密特触发adc
2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) Pub Date : 2022-06-12 DOI: 10.1109/vlsitechnologyandcir46769.2022.9830338
Shanshan Xie, Can Ni, P. Jain, F. Hamzaoglu, J. Kulkarni
{"title":"Gain-Cell CIM: Leakage and Bitline Swing Aware 2T1C Gain-Cell eDRAM Compute in Memory Design with Bitline Precharge DACs and Compact Schmitt Trigger ADCs","authors":"Shanshan Xie, Can Ni, P. Jain, F. Hamzaoglu, J. Kulkarni","doi":"10.1109/vlsitechnologyandcir46769.2022.9830338","DOIUrl":"https://doi.org/10.1109/vlsitechnologyandcir46769.2022.9830338","url":null,"abstract":"We present a leakage and read bitline (RBL) swing aware Compute-in-Memory (CIM) design leveraging a promising high-density gain-cell embedded DRAM bitcell and the intrinsic RBL capacitors to perform CIM computations within the limited RBL swing available in a 2T1C eDRAM. The CIM D/A converters (DAC) are realized intrinsically with variable RBL precharge voltage levels. A/D converters (ADC) are realized using Schmitt Triggers (ST) as compact and reconfigurable Flash comparators. A 65nm CMOS prototype achieves energy efficiency of 7.4-236 TOPS/W, 13.1-411 GOPS/mm2 for the CIFAR-10 dataset with ResNet-20 and improves the defined FoM by 2.3-4.3X over prior CIM designs.","PeriodicalId":332454,"journal":{"name":"2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115974913","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
First Fire-free, Low-voltage (~1.2 V), and Low Off-current (~3 nA) SiOxTey Selectors 第一款无火，低电压(~1.2 V)和低断流(~ 3na) sioxey选择器
2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) Pub Date : 2022-06-12 DOI: 10.1109/vlsitechnologyandcir46769.2022.9830395
S. Vaziri, I. Datye, E. Ambrosi, A. Khan, H. Kwon, C. H. Wu, C. Hsu, J. Guy, T. Y. Lee, H. P. Wong, X. Bao
{"title":"First Fire-free, Low-voltage (~1.2 V), and Low Off-current (~3 nA) SiOxTey Selectors","authors":"S. Vaziri, I. Datye, E. Ambrosi, A. Khan, H. Kwon, C. H. Wu, C. Hsu, J. Guy, T. Y. Lee, H. P. Wong, X. Bao","doi":"10.1109/vlsitechnologyandcir46769.2022.9830395","DOIUrl":"https://doi.org/10.1109/vlsitechnologyandcir46769.2022.9830395","url":null,"abstract":"Operating voltage compatibility and low power consumption are crucial for on-chip integration of high-density one-selector-one-resistor (1S/1R) arrays. However, traditional chalcogenide-based threshold selectors require a one-time first fire operation with voltage higher than the threshold voltage. Here, we introduce a novel SiOTe selector based on a stable silicon oxide matrix, with tunable first fire voltage and ultimately first fire-free characteristics. These selectors achieve low threshold voltages (Vth = 1.1 V – 1.5 V) and low off-current (Ioff ~ 3 nA at 0.5 V for Vth = 1.2 V). SiOTe selectors show promising thermal stability (300 °C, 30 min in air) and endurance of >108 cycles.","PeriodicalId":332454,"journal":{"name":"2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116348202","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A 3nm GAAFET Analog Assisted Digital LDO with High Current Density for Dynamic Voltage Scaling Mobile Applications 一种3nm GAAFET模拟辅助数字LDO，具有高电流密度，用于动态电压缩放移动应用
2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) Pub Date : 2022-06-12 DOI: 10.1109/vlsitechnologyandcir46769.2022.9830252
Seki Kim, Hyongmin Lee, Yongjin Lee, Dongha Lee, Byeongbae Lee, Jahoon Jin, Susie Kim, Miri Noh, K. Kang, Sangho Kim, Takahiro Nomiyama, Ji-Seon Paek, Jongwoo Lee
{"title":"A 3nm GAAFET Analog Assisted Digital LDO with High Current Density for Dynamic Voltage Scaling Mobile Applications","authors":"Seki Kim, Hyongmin Lee, Yongjin Lee, Dongha Lee, Byeongbae Lee, Jahoon Jin, Susie Kim, Miri Noh, K. Kang, Sangho Kim, Takahiro Nomiyama, Ji-Seon Paek, Jongwoo Lee","doi":"10.1109/vlsitechnologyandcir46769.2022.9830252","DOIUrl":"https://doi.org/10.1109/vlsitechnologyandcir46769.2022.9830252","url":null,"abstract":"This paper presents an analog assisted digital LDO achieving high current density and fast response characteristic. A current comparator based control method enables over 10x ratio of digital current over analog current for high current density regardless of PVT condition. The proposed LDO in 3nm GAAFET CMOS technology demonstrated current density of 34.15A/mm2 and fast transient characteristic of 38mV droop at 1A/1ns load current condition.","PeriodicalId":332454,"journal":{"name":"2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115385904","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
An 81.6dB SNDR 15.625MHz BW 3rd Order CT SDM with a True TI NS Quantizer 带True TI NS量化器的81.6dB SNDR 15.625MHz BW三阶CT SDM
2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) Pub Date : 2022-06-12 DOI: 10.1109/vlsitechnologyandcir46769.2022.9830207
Seungjong Lee, Taewook Kang, Seungheun Song, Kyumin Kwon, Michael J. Flynn
{"title":"An 81.6dB SNDR 15.625MHz BW 3rd Order CT SDM with a True TI NS Quantizer","authors":"Seungjong Lee, Taewook Kang, Seungheun Song, Kyumin Kwon, Michael J. Flynn","doi":"10.1109/vlsitechnologyandcir46769.2022.9830207","DOIUrl":"https://doi.org/10.1109/vlsitechnologyandcir46769.2022.9830207","url":null,"abstract":"This paper presents a continuous-time (CT) sigma-delta modulator (SDM) with a time-interleaved (TI) noise-shaping (NS) quantizer (QTZ). Complete parallelization of the NS QTZ operations relaxes loop filtering and residue integration and enables a high (6-bit) QTZ resolution. The 28nm CMOS prototype consumes 6.4mW at 500MS/s. The measured SNDR is 81.6dB for a 15.625MHz bandwidth. The corresponding Schreier FoMSNDR is 175.5dB.","PeriodicalId":332454,"journal":{"name":"2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114481632","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
First Demonstration of High-Sensitivity (NEP<1fW•Hz-1/2) Back-Illuminated Active-Matrix Deep UV Image Sensor by Monolithic Integration of Ga2O3 Photodetectors and Oxide Thin-Film-Transistors Ga2O3光电探测器和氧化薄膜晶体管单片集成的高灵敏度(NEP<1fW•Hz-1/2)背照有源矩阵深紫外图像传感器的首次演示
2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) Pub Date : 2022-06-12 DOI: 10.1109/vlsitechnologyandcir46769.2022.9830520
Yuan Qin, Congyan Lu, Zhaoan Yu, Zhihong Yao, F. Wu, Danian Dong, Xiaolong Zhao, Guangwei Xu, Yuhao Zhang, Shibing Long, Ling Li, Ming Liu
{"title":"First Demonstration of High-Sensitivity (NEP<1fW•Hz-1/2) Back-Illuminated Active-Matrix Deep UV Image Sensor by Monolithic Integration of Ga2O3 Photodetectors and Oxide Thin-Film-Transistors","authors":"Yuan Qin, Congyan Lu, Zhaoan Yu, Zhihong Yao, F. Wu, Danian Dong, Xiaolong Zhao, Guangwei Xu, Yuhao Zhang, Shibing Long, Ling Li, Ming Liu","doi":"10.1109/vlsitechnologyandcir46769.2022.9830520","DOIUrl":"https://doi.org/10.1109/vlsitechnologyandcir46769.2022.9830520","url":null,"abstract":"We, for the first time, demonstrated a back-illuminated active-matrix deep UV (DUV) image sensor by monolithically integrating an ultra-wide bandgap (UWBG) Ga2O3 photodetector (PD) array and IGZO thin-film-transistors (TFT) based on a low temperature back-end-of-line (BEOL) process. Benefited from the low off-state current of 10-13A, high on/off ratio of 5×108, and high stability of IGZO TFTs, the integrated PD/TFT sensor cell presents super-high sensitivity with NEP down to 1fW•Hz-1/2 with a high responsivity and specific detectivity of 302A/W and 1.7×1015Jones, respectively. The 32×32 DUV image sensor shows excellent uniformity and demonstrates a superior image recognition ability with light intensity down to 2 μW/cm2. This scalable, high-resolution DUV image sensor shows great promise for advanced imaging and machine vision applications.","PeriodicalId":332454,"journal":{"name":"2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121011594","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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