Chuei-Tang Wang, Chia-Chia Lin, Chih-Hsin Lu, Wei-Ting Chen, C. Tsai, Douglas C. H. Yu
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SoIC_H Technology for Heterogenous System Integration
An SoIC_H technology for 2.5D heterogeneous system integration is proposed. SoIC bond, replacing µbump, is used to provide low parasitic and high density of interconnects. Through system technology co-optimization (STCO), the proposed architecture provides over 60% power reduction for die-to-die I/O link and 81%, 14%, and 94% reductions in energy, latency, and area, respectively, for on-chip fanout design. For memory cubes, it introduces 61% latency and 49% energy reductions for 4-Hi SRAM cache and 30% bandwidth and 28% energy efficiency improvements for 12-Hi HBM.
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