C.-Y. Liao, K.-Y. Hsiang, Z.-F. Lou, Hsuan-Chi Tseng, C. Lin, Z.-X. Li, F.-C. Hsieh, C. C. Wang, Fu-Sheng Chang, Wei-Chang Ray, Y. Tseng, Shu-Tong Chang, T. C. Chen, M. Lee
{"title":"Endurance > 1011 Cycling of 3D GAA Nanosheet Ferroelectric FET with Stacked HfZrO2 to Homogenize Corner Field Toward Mitigate Dead Zone for High-Density eNVM","authors":"C.-Y. Liao, K.-Y. Hsiang, Z.-F. Lou, Hsuan-Chi Tseng, C. Lin, Z.-X. Li, F.-C. Hsieh, C. C. Wang, Fu-Sheng Chang, Wei-Chang Ray, Y. Tseng, Shu-Tong Chang, T. C. Chen, M. Lee","doi":"10.1109/vlsitechnologyandcir46769.2022.9830345","DOIUrl":"https://doi.org/10.1109/vlsitechnologyandcir46769.2022.9830345","url":null,"abstract":"After 1011 high endurance cycles with memory window (MW) =0.9 V is achieved for the 3D gate-all-around (GAA) nanosheet (NS) ferroelectric field-effect transistor (FeFET) based on double-HZO; the aim is to homogenize the corner field and mitigate dead zones. The interlayer Al2O3 or TiN in the double-HZO exhibits MW enhancement or low access voltage, respectively. The proposed MFMFS GAA-FeFET demonstrates a low VP/E = ±3.5 V (±2.3 MV/cm), large MW = 1.3 V, >1011 robust endurance cycles, and stable storage with data retention of >2×104 s; therefore, physical dimension scaling of the embedded nonvolatile memory (eNVM) is feasible for future generations.","PeriodicalId":332454,"journal":{"name":"2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129951666","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Qirui Zhang, Hyochan An, Zichen Fan, Zhehong Wang, Ziyun Li, Guanru Wang, Hun-Seok Kim, D. Blaauw, D. Sylvester
{"title":"A 22nm 3.5TOPS/W Flexible Micro-Robotic Vision SoC with 2MB eMRAM for Fully-on-Chip Intelligence","authors":"Qirui Zhang, Hyochan An, Zichen Fan, Zhehong Wang, Ziyun Li, Guanru Wang, Hun-Seok Kim, D. Blaauw, D. Sylvester","doi":"10.1109/vlsitechnologyandcir46769.2022.9830340","DOIUrl":"https://doi.org/10.1109/vlsitechnologyandcir46769.2022.9830340","url":null,"abstract":"We present a highly flexible micro-robotic vision SoC featuring a hybrid Processing Element (PE) for efficient processing of both Convolutional Neural Network (CNN) and non-CNN vision tasks with 2MB embedded MRAM for retentive fully-on-chip weight storage. Fabricated in 22nm, the design achieves 0.22nJ/pix for Harris corner detection (a non-CNN vision task) and 3.5TOPS/W (INT16) for CNN, a 60% efficiency improvement over state-of-the-art NVM-based NN ASICs.","PeriodicalId":332454,"journal":{"name":"2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128228433","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Ming-Yang Li, Ching-Hao Hsu, Shin-Wei Shen, Ang-Sheng Chou, Y. Lin, Chih-Piao Chuu, Ning Yang, Sui-An Chou, Lina Huang, Chao-Ching Cheng, W. Woon, S. Liao, Chih-I Wu, Lain‐Jong Li, I. Radu, H. P. Wong, Han Wang
{"title":"Wafer-Scale Bi-Assisted Semi-Auto Dry Transfer and Fabrication of High-Performance Monolayer CVD WS2 Transistor","authors":"Ming-Yang Li, Ching-Hao Hsu, Shin-Wei Shen, Ang-Sheng Chou, Y. Lin, Chih-Piao Chuu, Ning Yang, Sui-An Chou, Lina Huang, Chao-Ching Cheng, W. Woon, S. Liao, Chih-I Wu, Lain‐Jong Li, I. Radu, H. P. Wong, Han Wang","doi":"10.1109/vlsitechnologyandcir46769.2022.9830376","DOIUrl":"https://doi.org/10.1109/vlsitechnologyandcir46769.2022.9830376","url":null,"abstract":"A novel wafer-scale semi-automated dry transfer process for monolayer (1L) CVD WS2 was developed utilizing the weakly coupled interface between semimetal (Bi) and two-dimensional (2D) semiconductor (WS2). Bi semimetal serves as a gently adhesive transfer template for 2D materials, introducing minimal additional defects during the transfer process. Based on 2D materials processed using this new transfer method, semimetal-contacted (Bi and Sb) monolayer CVD WS2 nFETs were further demonstrated at wafer scale. Our CVD 1L WS2 nFETs fabricated using semimetal-assisted transfer with semimetal (Bi and Sb) contacts show record high on-current of 250 µA/µm and 243 µA/µm at VDS = 1 V, and record low contact resistance of 0.63 kΩ•µm and 0.73 kΩ•µm, respectively.","PeriodicalId":332454,"journal":{"name":"2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128885898","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
C. Safranski, G. Hu, J. Sun, P. Hashemi, S. Brown, L. Buzi, C. D'Emic, E. Edwards, E. Galligan, M. Gottwald, O. Gunawan, S. Karimeddiny, H. Jung, J. Kim, K. Latzko, P. Trouilloud, S. Zare, D. Worledge
{"title":"Reliable Sub-nanosecond MRAM with Double Spin-torque Magnetic Tunnel Junctions","authors":"C. Safranski, G. Hu, J. Sun, P. Hashemi, S. Brown, L. Buzi, C. D'Emic, E. Edwards, E. Galligan, M. Gottwald, O. Gunawan, S. Karimeddiny, H. Jung, J. Kim, K. Latzko, P. Trouilloud, S. Zare, D. Worledge","doi":"10.1109/vlsitechnologyandcir46769.2022.9830306","DOIUrl":"https://doi.org/10.1109/vlsitechnologyandcir46769.2022.9830306","url":null,"abstract":"We demonstrate reliable sub-nanosecond switching in two terminal STT-MRAM devices by using Double Spin-torque Magnetic Tunnel Junctions (DS-MTJs). Write-error-rate (WER) of 1E-6 was achieved in 194 devices with 250 ps write pulses and tight distributions. WER = 1E-6 was also demonstrated over a temperature range of -40°C to 85°C in a single device with 225 ps write pulses. No degradation was observed after 1E10 write cycles, written with 250 ps write pulses. We compare the DS-MTJ device switching performance to published results from state-of-the-art three terminal Spin-Orbit-Torque (SOT) MRAM devices and show a 10x reduction in switching current density (Jc) and 3-10x reduction in power consumption for devices with similar energy barriers (Eb).","PeriodicalId":332454,"journal":{"name":"2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131213520","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Jie Zhang, Wei Lu, Po-Tsang Huang, Sih-Han Li, Tsung-Yi Hung, Shih-Hsien Wu, M. Dai, I-Shan Chung, Wen-Chao Chen, Chin-Hung Wang, S. Sheu, Hung-Ming Chen, Kuan-Neng Chen, W. Lo, Chih-I Wu
{"title":"An Embedded Multi-Die Active Bridge (EMAB) Chip for Rapid-Prototype Programmable 2.5D/3D Packaging Technology","authors":"Jie Zhang, Wei Lu, Po-Tsang Huang, Sih-Han Li, Tsung-Yi Hung, Shih-Hsien Wu, M. Dai, I-Shan Chung, Wen-Chao Chen, Chin-Hung Wang, S. Sheu, Hung-Ming Chen, Kuan-Neng Chen, W. Lo, Chih-I Wu","doi":"10.1109/vlsitechnologyandcir46769.2022.9830188","DOIUrl":"https://doi.org/10.1109/vlsitechnologyandcir46769.2022.9830188","url":null,"abstract":"2.5D/3D integration combines multiple dies or chiplets into a single package through a silicon interposer and through-silicon-vias (TSVs). However, the wire routing of redistribution layer (RDL) on an interposer is time-consuming and expensive. Therefore, this work demonstrates the first programmable 2.5D/3D integration by an embedded multi-die active bridge (EMAB) chip for fast 2.5D/3D prototype proof. The EMAB chip is a programmable bridge and realized by a checkboard and super highways to connect I/Os of multiple dies. The control of programmable switches in EMAB is based on the information stored in the one-time programming (OTP) memory. To further improving the data rates of switches in the checkboard and super highway, a forward body-bias control is utilized to reduce the turn-on resistance. The maximum data rate of the super highway is up to 1Gbps and the data rate of the checkboard is 100Mbps through 20 I/O blocks. The proposed programmable advanced package technology is a fast time-to-market and low-cost 2.5D/3D integration solution for various IoT applications.","PeriodicalId":332454,"journal":{"name":"2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134536656","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Kaifei Chen, J. Niu, Guanhua Yang, Meng-xin Liu, Wendong Lu, Fuxi Liao, Kailiang Huang, Xinlv Duan, Congyan Lu, Jiawei Wang, Lingfei Wang, Mengmeng Li, Di Geng, Chao Zhao, Guilei Wang, Nianduan Lu, Ling Li, Ming Liu
{"title":"Scaling Dual-Gate Ultra-thin a-IGZO FET to 30 nm Channel Length with Record-high Gm,max of 559 µS/µm at VDS=1 V, Record-low DIBL of 10 mV/V and Nearly Ideal SS of 63 mV/dec","authors":"Kaifei Chen, J. Niu, Guanhua Yang, Meng-xin Liu, Wendong Lu, Fuxi Liao, Kailiang Huang, Xinlv Duan, Congyan Lu, Jiawei Wang, Lingfei Wang, Mengmeng Li, Di Geng, Chao Zhao, Guilei Wang, Nianduan Lu, Ling Li, Ming Liu","doi":"10.1109/vlsitechnologyandcir46769.2022.9830389","DOIUrl":"https://doi.org/10.1109/vlsitechnologyandcir46769.2022.9830389","url":null,"abstract":"We experimentally prove that amorphous IGZO FET can be scaled down by connected dual-gate design with enhanced electrostatic control. By connected dual-gate operation and scaled dual stacks, the short channel device (L<inf>CH</inf>=30 nm) achieves near ideal SS of 63 mV/dec and ultra-high on-state current (I<inf>ON</inf>) of 615 µA/µm at V<inf>GS</inf>-V<inf>TH</inf>=2 V&V<inf>DS</inf>=1 V. By this design, record-high transconductance (G<inf>m</inf>) of 559 µS/µm at V<inf>DS</inf>=1 V and record-low drain-induced-barrier-lowering (DIBL) of 10 mV/V are achieved, to our best knowledge, among all the a-IGZO transistors with sub-100 nm channel length reported so far.","PeriodicalId":332454,"journal":{"name":"2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131245076","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Zichen Fan, Hyochan An, Qirui Zhang, Boxun Xu, Li Xu, Chien-Wei Tseng, Yimai Peng, Ang Cao, Bowen Liu, Changwook Lee, Zhehong Wang, Fanghao Liu, Guanru Wang, S. Jiang, Hun-Seok Kim, D. Blaauw, D. Sylvester
{"title":"Audio and Image Cross-Modal Intelligence via a 10TOPS/W 22nm SoC with Back-Propagation and Dynamic Power Gating","authors":"Zichen Fan, Hyochan An, Qirui Zhang, Boxun Xu, Li Xu, Chien-Wei Tseng, Yimai Peng, Ang Cao, Bowen Liu, Changwook Lee, Zhehong Wang, Fanghao Liu, Guanru Wang, S. Jiang, Hun-Seok Kim, D. Blaauw, D. Sylvester","doi":"10.1109/vlsitechnologyandcir46769.2022.9830226","DOIUrl":"https://doi.org/10.1109/vlsitechnologyandcir46769.2022.9830226","url":null,"abstract":"We present an ultra-low-power multimedia signal processor (MMSP) SoC that integrates a versatile deep neural network (DNN) engine with audio and image signal processing accelerators for cross-modal IoT intelligence. The proposed MMSP features 2MB MRAM to store all DNN weights on-chip with an energy-efficient dataflow using an MRAM-cache and dynamic power gating. The SoC achieves up to 3-10 TOPS/W peak energy efficiency and consumes only 0.25-3.84 mW. Being the first to demonstrate CNN, GAN, and back-propagation (BP) on a single accelerator SoC for cross-modal fusion, it outperforms state-of-the-art DNN processors by 1.4 - 4.5× in energy efficiency.","PeriodicalId":332454,"journal":{"name":"2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133666590","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A Sparse Convolution Neural Network Accelerator for 3D/4D Point-Cloud Image Recognition on Low Power Mobile Device with Hopping-Index Rule Book for Efficient Coordinate Management","authors":"Qiankai Cao, Jie Gu","doi":"10.1109/vlsitechnologyandcir46769.2022.9830178","DOIUrl":"https://doi.org/10.1109/vlsitechnologyandcir46769.2022.9830178","url":null,"abstract":"This work presents the first 3D/4D sparse CNN (SCNN) accelerator for point cloud image recognition on low power devices. A special hopping-index rule book method and efficient data search technique were developed to mitigate the overhead of coordinate management for SCNN. A 65nm test chip for 3D/4D images was demonstrated with 7.09–13.6 TOPS/W power efficiency and state-of-the-art frame rate.","PeriodicalId":332454,"journal":{"name":"2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130058442","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
R. Acharya, A. Potočnik, S. Brebels, A. Grill, J. Verjauw, T. Ivanov, D. Lozano, D. Wan, F. Mohiyaddin, J. V. Damme, A. Vadiraj, M. Mongillo, G. Gielen, F. Catthoor, J. Craninckx, I. Radu, B. Govoreanu
{"title":"Scalable 1.4 μW cryo-CMOS SP4T multiplexer operating at 10 mK for high-fidelity superconducting qubit measurements","authors":"R. Acharya, A. Potočnik, S. Brebels, A. Grill, J. Verjauw, T. Ivanov, D. Lozano, D. Wan, F. Mohiyaddin, J. V. Damme, A. Vadiraj, M. Mongillo, G. Gielen, F. Catthoor, J. Craninckx, I. Radu, B. Govoreanu","doi":"10.1109/vlsitechnologyandcir46769.2022.9830396","DOIUrl":"https://doi.org/10.1109/vlsitechnologyandcir46769.2022.9830396","url":null,"abstract":"In this work, we report on the electrical performance of an ultra-low-power cryo-CMOS single-pole-4-throw (SP4T) RF multiplexer working at 10 mK base temperature stage of a dilution refrigerator. We use the multiplexer to benchmark a superconducting qubit for the very first time and obtain qubit coherence times of over 35 μs along with an average single-qubit gate fidelity of 99.93%, which exceeds the threshold required for quantum error-correction based on surface-code. This work demonstrates the operability of superconducting qubits with ultra-low-power cryo-CMOS devices at the base temperature, paving the way for advanced co-integration schemes.","PeriodicalId":332454,"journal":{"name":"2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114330224","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A Wireless Urine Detection System and Platform with Power-Efficient Electrochemical Readout ASIC and ABTS-CNT Biosensor","authors":"Shuenn-Yuh Lee, Hao-Yun Lee, Ding-Siang Ciou, Zhan-Xian Liao, Peng-Wei Huang, Y. Hsieh, Yi-Chieh Wei, Chia-Yu Lin, Meng-Dar Shieh, Ju-Yi Chen","doi":"10.1109/vlsitechnologyandcir46769.2022.9830325","DOIUrl":"https://doi.org/10.1109/vlsitechnologyandcir46769.2022.9830325","url":null,"abstract":"This work presents a wireless urine detection system and platform which consists of an electrochemical readout application specific integrated circuit (ASIC) and a biosensor composed of 2,2′-azino-bis(3-ethylbenzothiazoline-6-sulphonic acid) and carbon nanotube (ABTS-CNT) for the detection of urine albumin-to-creatinine ratio (UACR) on cardiovascular diseases healthcare system. The ASIC mainly includes a potentiostat with a current-sensing VCO-based continuous-time delta-sigma modulator (CTDSM) and a hybrid resistor-based digital-to-analog converter (R-DAC), which can be integrated with our developed dual-channel screen-printed carbon electrode (SPCE) for UACR detection. Experimental results have demonstrated the capability of the proposed urine detection system under practical urine tests.","PeriodicalId":332454,"journal":{"name":"2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115041775","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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