具有双自旋转矩磁隧道结的可靠亚纳秒MRAM

2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) Pub Date : 2022-06-12 DOI:10.1109/vlsitechnologyandcir46769.2022.9830306

C. Safranski, G. Hu, J. Sun, P. Hashemi, S. Brown, L. Buzi, C. D'Emic, E. Edwards, E. Galligan, M. Gottwald, O. Gunawan, S. Karimeddiny, H. Jung, J. Kim, K. Latzko, P. Trouilloud, S. Zare, D. Worledge

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引用次数: 5

摘要

我们利用双自旋转矩磁隧道结(DS-MTJs)在两个终端STT-MRAM器件中实现了可靠的亚纳秒开关。1E-6的写错误率(WER)在250 ps写脉冲和紧分布的194个器件上实现。WER = 1E-6也在-40°C至85°C的温度范围内进行了演示，在单个器件中具有225 ps的写入脉冲。在以250 ps写入脉冲写入1E10个写入周期后，没有观察到性能下降。我们将DS-MTJ器件的开关性能与已发表的最先进的三端自旋-轨道-扭矩(SOT) MRAM器件的结果进行了比较，结果显示，对于具有类似能量势垒(Eb)的器件，开关电流密度(Jc)降低了10倍，功耗降低了3-10倍。

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Reliable Sub-nanosecond MRAM with Double Spin-torque Magnetic Tunnel Junctions

We demonstrate reliable sub-nanosecond switching in two terminal STT-MRAM devices by using Double Spin-torque Magnetic Tunnel Junctions (DS-MTJs). Write-error-rate (WER) of 1E-6 was achieved in 194 devices with 250 ps write pulses and tight distributions. WER = 1E-6 was also demonstrated over a temperature range of -40°C to 85°C in a single device with 225 ps write pulses. No degradation was observed after 1E10 write cycles, written with 250 ps write pulses. We compare the DS-MTJ device switching performance to published results from state-of-the-art three terminal Spin-Orbit-Torque (SOT) MRAM devices and show a 10x reduction in switching current density (Jc) and 3-10x reduction in power consumption for devices with similar energy barriers (Eb).

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2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)

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