Shanshan Xie, Can Ni, P. Jain, F. Hamzaoglu, J. Kulkarni
{"title":"Gain-Cell CIM: Leakage and Bitline Swing Aware 2T1C Gain-Cell eDRAM Compute in Memory Design with Bitline Precharge DACs and Compact Schmitt Trigger ADCs","authors":"Shanshan Xie, Can Ni, P. Jain, F. Hamzaoglu, J. Kulkarni","doi":"10.1109/vlsitechnologyandcir46769.2022.9830338","DOIUrl":null,"url":null,"abstract":"We present a leakage and read bitline (RBL) swing aware Compute-in-Memory (CIM) design leveraging a promising high-density gain-cell embedded DRAM bitcell and the intrinsic RBL capacitors to perform CIM computations within the limited RBL swing available in a 2T1C eDRAM. The CIM D/A converters (DAC) are realized intrinsically with variable RBL precharge voltage levels. A/D converters (ADC) are realized using Schmitt Triggers (ST) as compact and reconfigurable Flash comparators. A 65nm CMOS prototype achieves energy efficiency of 7.4-236 TOPS/W, 13.1-411 GOPS/mm2 for the CIFAR-10 dataset with ResNet-20 and improves the defined FoM by 2.3-4.3X over prior CIM designs.","PeriodicalId":332454,"journal":{"name":"2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2022-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"9","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/vlsitechnologyandcir46769.2022.9830338","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 9
Abstract
We present a leakage and read bitline (RBL) swing aware Compute-in-Memory (CIM) design leveraging a promising high-density gain-cell embedded DRAM bitcell and the intrinsic RBL capacitors to perform CIM computations within the limited RBL swing available in a 2T1C eDRAM. The CIM D/A converters (DAC) are realized intrinsically with variable RBL precharge voltage levels. A/D converters (ADC) are realized using Schmitt Triggers (ST) as compact and reconfigurable Flash comparators. A 65nm CMOS prototype achieves energy efficiency of 7.4-236 TOPS/W, 13.1-411 GOPS/mm2 for the CIFAR-10 dataset with ResNet-20 and improves the defined FoM by 2.3-4.3X over prior CIM designs.