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2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)最新文献

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Imager with Dynamic LSB Adaptation and Ratiometric Readout for Low-Bit Depth 5-μW Peak Power in Purely-Harvested Systems 具有动态LSB自适应和纯采集系统低位深度5 μ w峰值功率比例读出的成像仪
2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) Pub Date : 2022-06-12 DOI: 10.1109/vlsitechnologyandcir46769.2022.9830147
K. Ahmed, Longyang Lin, P. Salamani, M. Alioto
{"title":"Imager with Dynamic LSB Adaptation and Ratiometric Readout for Low-Bit Depth 5-μW Peak Power in Purely-Harvested Systems","authors":"K. Ahmed, Longyang Lin, P. Salamani, M. Alioto","doi":"10.1109/vlsitechnologyandcir46769.2022.9830147","DOIUrl":"https://doi.org/10.1109/vlsitechnologyandcir46769.2022.9830147","url":null,"abstract":"An imager with μW peak power is introduced for purely-harvested operation. The LSB is dynamically adapted to the light intensity of the scene for aggressive bit depth downscaling, avoiding traditional dynamic range over-margining across practical light intensities under fixed LSB. Ratiometric readout of pixel current cancels threshold voltage mismatch. A 256×256-pixel 180-nm imager shows 5-μW power at 1 fps and 4 bits, while keeping ImageNet classification accuracy drop to percentage points under 75-dB ambient light range, across original and brightness-adjusted images.","PeriodicalId":332454,"journal":{"name":"2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125837025","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Interfacial-Layer Design for Hf1-xZrxO2-Based FTJ Devices: From Atom to Array 基于hf1 - xzrxo2的FTJ器件的接口层设计:从原子到阵列
2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) Pub Date : 2022-06-12 DOI: 10.1109/vlsitechnologyandcir46769.2022.9830462
H. Chiang, J. Wang, Kuan‐Heng Lin, C. Nien, J. Wu, K.-Y. Hsiang, Chih-Piao Chuu, Y.-W. Chen, X. W. Zhang, C. Liu, Tahui Wang, C. -. Wang, M. Lee, M. Chang, C. Chang, T. C. Chen
{"title":"Interfacial-Layer Design for Hf1-xZrxO2-Based FTJ Devices: From Atom to Array","authors":"H. Chiang, J. Wang, Kuan‐Heng Lin, C. Nien, J. Wu, K.-Y. Hsiang, Chih-Piao Chuu, Y.-W. Chen, X. W. Zhang, C. Liu, Tahui Wang, C. -. Wang, M. Lee, M. Chang, C. Chang, T. C. Chen","doi":"10.1109/vlsitechnologyandcir46769.2022.9830462","DOIUrl":"https://doi.org/10.1109/vlsitechnologyandcir46769.2022.9830462","url":null,"abstract":"For the first time, we demonstrate Ferroelectric Tunneling Junctions (FTJs) with both (a) 10-year retention time projected from measured data and (b) robust endurance (> 108 cycles) with the on-off ratio >10× by inserting a 1.8nm Al2O3 interfacial layer (IL) into the FTJs. Compared with Metal-Ferroelectric-Metal (MFM) FTJs, higher orthorhombic phase (~6×) was verified by physical analyses and first-principles calculations in our proposed Metal-Ferroelectric-IL-Metal (MFIM) FTJs, resulting in the remanent polarization (2Pr) which improves the retention and the on-off ratio significantly.","PeriodicalId":332454,"journal":{"name":"2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120850434","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Low-capacitance Ultrathin InGaAs Membrane Photodetector on Si Slot Waveguide towards Receiver-less System 面向无接收机系统的Si槽波导低电容超薄InGaAs薄膜光电探测器
2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) Pub Date : 2022-06-12 DOI: 10.1109/vlsitechnologyandcir46769.2022.9830204
Tomohiro Akazawa, D. Wu, Kai Sumita, N. Sekine, M. Okano, K. Toprasertpong, Shinichi Takagi, M. Takenaka
{"title":"Low-capacitance Ultrathin InGaAs Membrane Photodetector on Si Slot Waveguide towards Receiver-less System","authors":"Tomohiro Akazawa, D. Wu, Kai Sumita, N. Sekine, M. Okano, K. Toprasertpong, Shinichi Takagi, M. Takenaka","doi":"10.1109/vlsitechnologyandcir46769.2022.9830204","DOIUrl":"https://doi.org/10.1109/vlsitechnologyandcir46769.2022.9830204","url":null,"abstract":"We proposed a Si/III-V hybrid waveguide photodetector consisting of an ultrathin InGaAs membrane and Si slot waveguide, enabling low capacitance and high responsivity simultaneously. The strong optical confinement in a Si slot waveguide enhanced optical absorption in the InGaAs membrane. As a result, we successfully demonstrated high responsivity of 1 A/W and sufficiently small capacitance of 1.9 fF to realize a receiver-less (TIA-less) system.","PeriodicalId":332454,"journal":{"name":"2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124385139","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A 17–95.6 TOPS/W Deep Learning Inference Accelerator with Per-Vector Scaled 4-bit Quantization for Transformers in 5nm 一种17-95.6 TOPS/W深度学习推理加速器，用于5nm变压器的逐向量缩放4位量化
2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) Pub Date : 2022-06-12 DOI: 10.1109/vlsitechnologyandcir46769.2022.9830277
Ben Keller, Rangharajan Venkatesan, Steve Dai, S. Tell, B. Zimmer, W. Dally, C. T. Gray, Brucek Khailany
{"title":"A 17–95.6 TOPS/W Deep Learning Inference Accelerator with Per-Vector Scaled 4-bit Quantization for Transformers in 5nm","authors":"Ben Keller, Rangharajan Venkatesan, Steve Dai, S. Tell, B. Zimmer, W. Dally, C. T. Gray, Brucek Khailany","doi":"10.1109/vlsitechnologyandcir46769.2022.9830277","DOIUrl":"https://doi.org/10.1109/vlsitechnologyandcir46769.2022.9830277","url":null,"abstract":"We present a deep neural network (DNN) accelerator designed for efficient execution of transformer-based DNNs, which have become ubiquitous for natural language processing tasks. DNN inference accelerators often employ specialized hardware techniques such as reduced precision to improve energy efficiency, but many of these techniques result in catastrophic accuracy loss on transformers. The proposed accelerator supports per-vector scaled quantization and approximate softmax to enable the use of 4-bit arithmetic with little accuracy loss. The 5nm prototype achieves 95.6 TOPS/W in benchmarking and 1711 inferences/s/W with only 0.7% accuracy loss on BERT, demonstrating a practical accelerator design for energy-efficient inference with transformers.","PeriodicalId":332454,"journal":{"name":"2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127911321","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
Optimal Cell Structure/Operation Design of 3D Semicircular Split-gate Cells for Ultra-high-density Flash Memory 超高密度闪存三维半圆形分栅单元的优化结构/操作设计
2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) Pub Date : 2022-06-12 DOI: 10.1109/vlsitechnologyandcir46769.2022.9830513
T. Morooka, T. Ishikawa, M. Komura, T. Kato, Y. Koyama, Y. Han, Y. Sugawara, D. Kuwabara, Y. Arayashiki, A. Murayama, K. Nishiyama, K. Sugimae, T. Ogura, H. Takeda, N. Kariya, Y. Goki, S. Konuma, Y. Kamiya, H. Yamashita, H. Shiga, K. Itagaki, R. Tanaka, T. Maeda, N. Ohtani, M. Fujiwara
{"title":"Optimal Cell Structure/Operation Design of 3D Semicircular Split-gate Cells for Ultra-high-density Flash Memory","authors":"T. Morooka, T. Ishikawa, M. Komura, T. Kato, Y. Koyama, Y. Han, Y. Sugawara, D. Kuwabara, Y. Arayashiki, A. Murayama, K. Nishiyama, K. Sugimae, T. Ogura, H. Takeda, N. Kariya, Y. Goki, S. Konuma, Y. Kamiya, H. Yamashita, H. Shiga, K. Itagaki, R. Tanaka, T. Maeda, N. Ohtani, M. Fujiwara","doi":"10.1109/vlsitechnologyandcir46769.2022.9830513","DOIUrl":"https://doi.org/10.1109/vlsitechnologyandcir46769.2022.9830513","url":null,"abstract":"Three-dimensional (3D) semicircular split-gate floating-gate (FG) cells have been successfully developed for both boosting cell density per footprint and expanding the capability of multiple bits per cell. FG structure engineering mitigates program/erase (P/E) window reduction due to the fringing field effect in the split-gate cell. Front-side and back-side cells which share the same channel can be separately read by reducing back-side cell leakage current by means of back-gate bias control. Moreover, FG structure enables tight Vth distribution by suppressing random telegraph noise (RTN) increase due to small cell area. As a result, the distributions of four bits/cell (QLC) and five bits/cell (PLC) have been experimentally demonstrated by the split-gate cell arrays for the first time.","PeriodicalId":332454,"journal":{"name":"2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129151052","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Fully Integrated 2x2 MIMO Real Simultaneous Dual Band WiFi CMOS Power Amplifiers With a Single Inductor Multiple Output Supply Modulation Technique 全集成2x2 MIMO实时同步双频WiFi CMOS功率放大器，采用单电感多输出电源调制技术
2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) Pub Date : 2022-06-12 DOI: 10.1109/vlsitechnologyandcir46769.2022.9830469
Ji-Seon Paek, Jeongkwan Lee, Wan Kim, Jun-Suk Bang, Jongwoo Lee
{"title":"Fully Integrated 2x2 MIMO Real Simultaneous Dual Band WiFi CMOS Power Amplifiers With a Single Inductor Multiple Output Supply Modulation Technique","authors":"Ji-Seon Paek, Jeongkwan Lee, Wan Kim, Jun-Suk Bang, Jongwoo Lee","doi":"10.1109/vlsitechnologyandcir46769.2022.9830469","DOIUrl":"https://doi.org/10.1109/vlsitechnologyandcir46769.2022.9830469","url":null,"abstract":"This paper presents fully integrated 2x2 MIMO dual-band CMOS power amplifiers with a simultaneous multiple PA supply voltage modulation technique using a switched-capacitor (SC)-based single inductor multiple output (SIMO) DC-DC converter. For 802.11ax MCS11 160/40MHz signals, the designed A/G-band CMOS PAs using the proposed supply modulation scheme achieve -40dB EVM at 15.7/18.5dBm output power and save 340/334mW of dc power consumption compared to 3.3V fixed supply voltage PA, respectively.","PeriodicalId":332454,"journal":{"name":"2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126975192","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Perspective on Low-dimensional Channel Materials for Extremely Scaled CMOS 极尺度CMOS低维通道材料研究进展
2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) Pub Date : 2022-06-12 DOI: 10.1109/vlsitechnologyandcir46769.2022.9830447
S. Su, E. Chen, T. Hung, Mengyao Li, G. Pitner, Chao-Ching Cheng, Han Wang, J. Cai, H. P. Wong, I. Radu
{"title":"Perspective on Low-dimensional Channel Materials for Extremely Scaled CMOS","authors":"S. Su, E. Chen, T. Hung, Mengyao Li, G. Pitner, Chao-Ching Cheng, Han Wang, J. Cai, H. P. Wong, I. Radu","doi":"10.1109/vlsitechnologyandcir46769.2022.9830447","DOIUrl":"https://doi.org/10.1109/vlsitechnologyandcir46769.2022.9830447","url":null,"abstract":"Low-dimensional materials (LDMs) such as two-dimensional transition metal dichalcogenides (2D TMDs) and carbon nanotubes (CNTs) have the potential to be the channel material in extremely scaled CMOS transistors. Based on current hardware data, the design space for contacted-gate pitch (CGP) scaled transistors is explored for these materials. The ON current, sources of leakage which limit OFF current, and CGP scaling potential are analyzed by separately considering effects from shrinking the gate length, contact length, and extension length. Doping of LDM is the main challenge to reduce contact and extension resistance for scaled transistors. Experimental control of p-type doping of 2D is reported as an example of doping impact.","PeriodicalId":332454,"journal":{"name":"2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131007288","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
5G mmWave Power Amplifier and Low-Noise Amplifier in 300mm GaN-on-Si Technology 5G毫米波功率放大器和300mm GaN-on-Si技术的低噪声放大器
2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) Pub Date : 2022-06-12 DOI: 10.1109/vlsitechnologyandcir46769.2022.9830383
Q. Yu, H. Then, D. Thomson, Jessica C. Chou, Jeffrey Garrett, I-Lun Huang, I. Momson, Surej Ravikumar, Seahee Hwangbo, A. Latorre-Rey, Ananda Roy, M. Radosavljevic, M. Beumer, P. Koirala, N. Thomas, N. Nair, H. Vora, S. Bader, J. Rode, J. Jensen, S. Rami
{"title":"5G mmWave Power Amplifier and Low-Noise Amplifier in 300mm GaN-on-Si Technology","authors":"Q. Yu, H. Then, D. Thomson, Jessica C. Chou, Jeffrey Garrett, I-Lun Huang, I. Momson, Surej Ravikumar, Seahee Hwangbo, A. Latorre-Rey, Ananda Roy, M. Radosavljevic, M. Beumer, P. Koirala, N. Thomas, N. Nair, H. Vora, S. Bader, J. Rode, J. Jensen, S. Rami","doi":"10.1109/vlsitechnologyandcir46769.2022.9830383","DOIUrl":"https://doi.org/10.1109/vlsitechnologyandcir46769.2022.9830383","url":null,"abstract":"This paper presents fully integrated power amplifier (PA) and low-noise amplifier (LNA) targeting 5G mmWave band n260 (37GHz-40GHz) in 300mm GaN-on-Si technology. At 39.5GHz, the PA achieves measured Psat, peak PAE, linear gain, and OP1dB of 25dBm, 38.8%, 24.8dB, and 19.8dBm, occupying only 0.079mm2. The LNA achieves 24.6dB gain, 2.9dB noise figure, and -11.4dBm IIP3 at 38GHz. Both circuits are compact and viable candidates for phased arrays in mobile devices. This is industry’s first demonstration of mmWave circuits in 300mm GaN-on-Si technology.","PeriodicalId":332454,"journal":{"name":"2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131282379","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Specificities of linear Si QD arrays integration and characterization 线性硅量子点阵列的特性集成与表征
2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) Pub Date : 2022-06-12 DOI: 10.1109/vlsitechnologyandcir46769.2022.9830352
H. Niebojewski, B. Bertrand, E. Nowak, T. Bedecarrats, B. C. Paz, L. Contamin, P. Mortemousque, V. Labracherie, L. Brevard, H. Sahin, J. Charbonnier, C. Thomas, M. Assous, M. Cassé, M. Urdampilleta, Y. Niquet, F. Perruchot, F. Gaillard, S. D. Franceschi, T. Meunier, M. Vinet
{"title":"Specificities of linear Si QD arrays integration and characterization","authors":"H. Niebojewski, B. Bertrand, E. Nowak, T. Bedecarrats, B. C. Paz, L. Contamin, P. Mortemousque, V. Labracherie, L. Brevard, H. Sahin, J. Charbonnier, C. Thomas, M. Assous, M. Cassé, M. Urdampilleta, Y. Niquet, F. Perruchot, F. Gaillard, S. D. Franceschi, T. Meunier, M. Vinet","doi":"10.1109/vlsitechnologyandcir46769.2022.9830352","DOIUrl":"https://doi.org/10.1109/vlsitechnologyandcir46769.2022.9830352","url":null,"abstract":"The low temperature operation of quantum computing devices implies developing characterization protocols, from extensive statistical tests to targeted device screening at cryogenic temperature. This paper reviews major integration constraints arising in linear Si quantum dots arrays and their implication on both the device operation and electrical characterization.","PeriodicalId":332454,"journal":{"name":"2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132814949","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A 3V 15b 157μW Cryo-CMOS DAC for Multiplexed Spin-Qubit Biasing 用于多路自旋-量子位偏置的3V 15b 157μW Cryo-CMOS DAC
2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) Pub Date : 2022-06-12 DOI: 10.1109/vlsitechnologyandcir46769.2022.9830309
Luc Enthoven, J. V. Staveren, Jiang Gong, M. Babaie, F. Sebastiano
{"title":"A 3V 15b 157μW Cryo-CMOS DAC for Multiplexed Spin-Qubit Biasing","authors":"Luc Enthoven, J. V. Staveren, Jiang Gong, M. Babaie, F. Sebastiano","doi":"10.1109/vlsitechnologyandcir46769.2022.9830309","DOIUrl":"https://doi.org/10.1109/vlsitechnologyandcir46769.2022.9830309","url":null,"abstract":"This paper presents a 15b cryo-CMOS DAC for multiplexed spin-qubit biasing implemented in a 22-nm FinFET process. The integrating-DAC architecture and the robust digitally-assisted high-voltage output stage enable a low power dissipation (157μW) and small area (0.08mm2) independent of the number of biased qubits, and a 3V output range well beyond the nominal supply. This represents the first scalable solution for cryo-CMOS qubit biasing, which achieves a 1.8× better voltage resolution with a lower DNL over a 3× larger output range than the current state-of-the-art.","PeriodicalId":332454,"journal":{"name":"2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133490307","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
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