Optimal Cell Structure/Operation Design of 3D Semicircular Split-gate Cells for Ultra-high-density Flash Memory

2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) Pub Date : 2022-06-12 DOI:10.1109/vlsitechnologyandcir46769.2022.9830513

T. Morooka, T. Ishikawa, M. Komura, T. Kato, Y. Koyama, Y. Han, Y. Sugawara, D. Kuwabara, Y. Arayashiki, A. Murayama, K. Nishiyama, K. Sugimae, T. Ogura, H. Takeda, N. Kariya, Y. Goki, S. Konuma, Y. Kamiya, H. Yamashita, H. Shiga, K. Itagaki, R. Tanaka, T. Maeda, N. Ohtani, M. Fujiwara

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Abstract

Three-dimensional (3D) semicircular split-gate floating-gate (FG) cells have been successfully developed for both boosting cell density per footprint and expanding the capability of multiple bits per cell. FG structure engineering mitigates program/erase (P/E) window reduction due to the fringing field effect in the split-gate cell. Front-side and back-side cells which share the same channel can be separately read by reducing back-side cell leakage current by means of back-gate bias control. Moreover, FG structure enables tight Vth distribution by suppressing random telegraph noise (RTN) increase due to small cell area. As a result, the distributions of four bits/cell (QLC) and five bits/cell (PLC) have been experimentally demonstrated by the split-gate cell arrays for the first time.

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超高密度闪存三维半圆形分栅单元的优化结构/操作设计

三维(3D)半圆分栅浮栅(FG)单元已经成功开发，既可以提高每个单元的密度，又可以扩展每个单元的多比特容量。FG结构工程减轻了由于分栅单元中的边缘场效应而导致的程序/擦除(P/E)窗口减小。通过后门偏置控制减少背面电池漏电流，可以将共用同一通道的前后电池分开读取。此外，FG结构通过抑制由于小区面积小而增加的随机电报噪声(RTN)，使Vth分布紧密。实验结果表明，四比特/单元(QLC)和五比特/单元(PLC)的分布首次得到了实验证明。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)

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