2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)最新文献_第6页

PPAC of sheet-based CFET configurations for 4 track design with 16nm metal pitch PPAC基于薄片的cfeet配置，采用16nm金属间距的4轨设计

2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) Pub Date : 2022-06-12 DOI: 10.1109/vlsitechnologyandcir46769.2022.9830492

P. Schuddinck, F. M. Bufler, Y. Xiang, A. Farokhnejad, G. Mirabelli, A. Vandooren, B. Chehab, A. Gupta, C. Neve, G. Hellings, J. Ryckaert

引用次数: 12

BEOL Compatible Ferroelectric Routers for Run-time Reconfigurable Compute-in-Memory Accelerators 用于运行时可重构内存中计算加速器的BEOL兼容铁电路由器

2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) Pub Date : 2022-06-12 DOI: 10.1109/vlsitechnologyandcir46769.2022.9830498

A. Khanna, H. Ye, Y. Luo, G. Bajpai, M. Jose, W. Chakraborty, Shimeng Yu, P. Fay, S. Datta

{"title":"BEOL Compatible Ferroelectric Routers for Run-time Reconfigurable Compute-in-Memory Accelerators","authors":"A. Khanna, H. Ye, Y. Luo, G. Bajpai, M. Jose, W. Chakraborty, Shimeng Yu, P. Fay, S. Datta","doi":"10.1109/vlsitechnologyandcir46769.2022.9830498","DOIUrl":"https://doi.org/10.1109/vlsitechnologyandcir46769.2022.9830498","url":null,"abstract":"Compute-in-memory (CIM) accelerators based on run-time reconfigurable designs have shown great promise in speeding up deep neural network (DNN) inferencing. Here, we present back-end-of-the-line (BEOL) compatible Indium Tungsten Oxide channel ferroelectric transistors (IWO FeFET) as signal routing switches (RS) for monolithic 3D (M3D) CIM accelerator. We demonstrate 2.45 GHz measured cutoff frequency (fT) for the transistor and greater than 11.5 GHz intrinsic fT by de-embedding transistor extrinsic parasitics obtained through developed small-signal equivalent circuit model. Pass-transistor configuration measurements show less than 250ps of added delay and 15dB of isolation at 2.5GHz between programmed and erased states. Run-time reconfigurable operation of a 4-way routing switch is experimentally demonstrated with excellent selectivity and endurance greater than 1010 cycles. System level benchmarking of a M3D CIM accelerator employing IWO FeFET RS and weights performed on real-word DNN models shows 2.5x improvement in energy efficiency and >10% gain in area efficiency compared to 7nm SRAM design.","PeriodicalId":332454,"journal":{"name":"2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124735902","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

A Wafer Scale Hybrid Integration Platform for Co-packaged Photonics using a CMOS based Optical InterposerTM 基于CMOS的光介面器的晶圆级混合集成平台

2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) Pub Date : 2022-06-12 DOI: 10.1109/vlsitechnologyandcir46769.2022.9830432

S. Venkatesan, James Lee, S. Goh, B. Pile, Daniel Meerovich, J. Mo, Yang Jing, Lucas Soldano, Baochang Xu, Yu Zhang, A. Thean, Yeow Kheng Lim

引用次数: 4

Wafer Level Pixelation of Colloidal Quantum Dot Image Sensors 胶体量子点图像传感器的晶圆级像素化

2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) Pub Date : 2022-06-12 DOI: 10.1109/vlsitechnologyandcir46769.2022.9830334

Yunlong Li, G. Karve, P. Malinowski, J. Kim, Epimitheas Georgitzikis, V. Pejović, M. Lim, L. M. Hagelsieb, R. Puybaret, I. Lieberman, Jiwon Lee, D. Cheyns, P. Heremans, H. Osman, D. Tezcan

引用次数: 0

First Demonstration of 1-bit Erase in Vertical NAND Flash Memory 垂直NAND闪存中1位擦除的首次演示

2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) Pub Date : 2022-06-12 DOI: 10.1109/vlsitechnologyandcir46769.2022.9830445

Honam Yoo, Jong-Won Back, Nam-Hun Kim, D. Kwon, Byung-Gook Park, Jong-Ho Lee

引用次数: 2

300 mm Wafer-scale In-situ CVD Growth Achieving 5.1×10-10 Ω-cm2 P-Type Contact Resistivity: Record 2.5×1021 cm-3 Active Doping and Demonstration on Highly-Scaled 3D Structures 300 mm晶圆级原位CVD生长实现5.1×10-10 Ω-cm2 p型接触电阻率:记录2.5×1021 cm-3活性掺杂和高尺度三维结构的演示

2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) Pub Date : 2022-06-12 DOI: 10.1109/vlsitechnologyandcir46769.2022.9830220

Haiwen Xu, R. Khazaka, Jishen Zhang, Zijie Zheng, Yue Chen, Xiao Gong

引用次数: 1

A Relative-Prime Rotation Based Fully On-Chip Background Skew Calibration for Time-Interleaved ADCs 基于相对素数旋转的时间交错adc全片上背景偏斜校准

2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) Pub Date : 2022-06-12 DOI: 10.1109/vlsitechnologyandcir46769.2022.9830416

Dong-Jin Chang, S. Ryu

引用次数: 0

Demonstration of 3D sequential FD-SOI on CMOS FinFET stacking featuring low temperature Si layer transfer and top tier device fabrication with tier interconnections 3D顺序FD-SOI在CMOS FinFET堆叠上的演示，具有低温Si层转移和层互连的顶层器件制造

2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) Pub Date : 2022-06-12 DOI: 10.1109/vlsitechnologyandcir46769.2022.9830400

A. Vandooren, N. Parihar, J. Franco, R. Loo, H. Arimura, R. Rodriguez, F. Sebaai, S. Iacovo, K. Vandersmissen, W. Li, G. Mannaert, D. Radisic, E. Rosseel, A. Hikavyy, A. Jourdain, O. Mourey, G. Gaudin, S. Reboh, L. Van-Jodin, G. Besnard, C. Neve, Bich-Yen Nguyen, I. Radu, E. Litta, N. Horiguchi

{"title":"Demonstration of 3D sequential FD-SOI on CMOS FinFET stacking featuring low temperature Si layer transfer and top tier device fabrication with tier interconnections","authors":"A. Vandooren, N. Parihar, J. Franco, R. Loo, H. Arimura, R. Rodriguez, F. Sebaai, S. Iacovo, K. Vandersmissen, W. Li, G. Mannaert, D. Radisic, E. Rosseel, A. Hikavyy, A. Jourdain, O. Mourey, G. Gaudin, S. Reboh, L. Van-Jodin, G. Besnard, C. Neve, Bich-Yen Nguyen, I. Radu, E. Litta, N. Horiguchi","doi":"10.1109/vlsitechnologyandcir46769.2022.9830400","DOIUrl":"https://doi.org/10.1109/vlsitechnologyandcir46769.2022.9830400","url":null,"abstract":"3D sequential stacking is demonstrated using top tier FDSOI devices on bottom tier bulk finFETs. 3D integration and top-bottom layer interconnectivity is validated through functional 3D via chains, 3D CMOS single inverters and inverter chain with transistors built in the top and bottom layers. Three different Si layer transfer flows, including a low temperature Smart Cut™, are investigated and compared electrically for top tier planar devices. Transfer of bi-axial tensile strained silicon is demonstrated with a 60-80% performance boost of the top tier nMOS device over the unstrained silicon devices. Further process optimization of the low temperature Smart Cut™ transfer provided significant electron and hole mobility recovery of the top tier devices. Impact of the stacking on bottom tier finFET devices is also studied for various bottom gate stacks.","PeriodicalId":332454,"journal":{"name":"2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125771863","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

A Packaged 90-to-96GHz 16-Element Phased Array with 18.8/15.8dBm Psat/OP1dB, 14.8% TX PAE in 65nm CMOS Process and +51dBm Array EIRP 封装的90至96ghz 16元相控阵，Psat/OP1dB为18.8/15.8dBm, 65nm CMOS工艺的TX PAE为14.8%，阵列EIRP为+51dBm

2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) Pub Date : 2022-06-12 DOI: 10.1109/vlsitechnologyandcir46769.2022.9830350

Wei Zhu, Jian Zhang, Jiawen Wang, Ruitao Wang, Chenguang Li, Kaiyang Wang, Yan Wang

引用次数: 1

Selective operations of multi-pillar SOT-MRAM for high density and low power embedded memories 用于高密度低功耗嵌入式存储器的多柱SOT-MRAM的选择性操作

2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) Pub Date : 2022-06-12 DOI: 10.1109/vlsitechnologyandcir46769.2022.9830307

K. Cai, S. V. Beek, S. Rao, K. Fan, M. Gupta, V. Nguyen, G. Jayakumar, G. Talmelli, S. Couet, G. Kar

引用次数: 8