PPAC基于薄片的cfeet配置，采用16nm金属间距的4轨设计

2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) Pub Date : 2022-06-12 DOI:10.1109/vlsitechnologyandcir46769.2022.9830492

P. Schuddinck, F. M. Bufler, Y. Xiang, A. Farokhnejad, G. Mirabelli, A. Vandooren, B. Chehab, A. Gupta, C. Neve, G. Hellings, J. Ryckaert

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引用次数: 12

摘要

我们评估了纳米片(NS)，叉片(FS)，单片和顺序互补FET (cet)在5和4磁道(T)设计下的功率-性能-面积和成本(PPAC)，具有紧密的栅极间距(CPP)和金属间距(MP)。虽然NS和FS被证明不适合4T设计，但cfet提供了高性能且具有成本效益的4T解决方案。

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PPAC of sheet-based CFET configurations for 4 track design with 16nm metal pitch

We evaluate Power-Performance-Area & Cost (PPAC) for nanosheet (NS), forksheet (FS), monolithic & sequential Complementary FET (CFET) at 5 & 4 track (T) designs with tight gate pitch (CPP) & metal pitch (MP). While NS & FS prove unsuitable for 4T designs, CFETs provide a performant & cost-effective 4T solution.

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2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)

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