基于相对素数旋转的时间交错adc全片上背景偏斜校准

2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) Pub Date : 2022-06-12 DOI:10.1109/vlsitechnologyandcir46769.2022.9830416

Dong-Jin Chang, S. Ryu

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引用次数: 0

摘要

提出了一种基于相对素旋转(RPR)自相关计算的时间交错(TI) adc的片上背景偏度校准技术，该技术可以更灵活地选择通道数，且不存在残余偏度积累。采用全片上校准的8 × TI 10b 1.4GS/s原型ADC在Nyquist输入下的SNDR为48.2dB，在28纳米FDSOI中FoM为33 fJ/c-s。片上校准电路仅占adc核心功耗的24%。

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A Relative-Prime Rotation Based Fully On-Chip Background Skew Calibration for Time-Interleaved ADCs

An on-chip background skew calibration technique for time-interleaved (TI) ADCs with relative-prime rotation (RPR) based autocorrelation computation is presented, with which more flexible choice of number of channels and no residual skew accumulation are realized. An 8 × TI 10b 1.4GS/s prototype ADC with fully on-chip calibration achieves an SNDR of 48.2dB at over Nyquist input and a FoM of 33 fJ/c-s in 28-nm FDSOI. The on-chip calibration circuitry takes only 24% of the ADC-core power consumption.

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来源期刊

2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)

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