P. Schuddinck, F. M. Bufler, Y. Xiang, A. Farokhnejad, G. Mirabelli, A. Vandooren, B. Chehab, A. Gupta, C. Neve, G. Hellings, J. Ryckaert
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引用次数: 12
Abstract
We evaluate Power-Performance-Area & Cost (PPAC) for nanosheet (NS), forksheet (FS), monolithic & sequential Complementary FET (CFET) at 5 & 4 track (T) designs with tight gate pitch (CPP) & metal pitch (MP). While NS & FS prove unsuitable for 4T designs, CFETs provide a performant & cost-effective 4T solution.