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2010 International Conference on Simulation of Semiconductor Processes and Devices最新文献

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Molecular dynamics simulation on LO phonon mode decay in Si nano-structure covered with oxide films 氧化膜覆盖硅纳米结构中LO声子模式衰减的分子动力学模拟
2010 International Conference on Simulation of Semiconductor Processes and Devices Pub Date : 2010-10-14 DOI: 10.1109/SISPAD.2010.5604568
T. Zushi, I. Ohdomari, T. Watanabe, Y. Kamakura, K. Taniguchi
{"title":"Molecular dynamics simulation on LO phonon mode decay in Si nano-structure covered with oxide films","authors":"T. Zushi, I. Ohdomari, T. Watanabe, Y. Kamakura, K. Taniguchi","doi":"10.1109/SISPAD.2010.5604568","DOIUrl":"https://doi.org/10.1109/SISPAD.2010.5604568","url":null,"abstract":"A series of molecular dynamics (MD) simulations is conducted to investigate the dynamics of longitudinal optical (LO) phonon in Si nano-structure confined with oxide films. This work is motivated by heat issues in nanoscopic devices; it is considered that the LO phonons with low group velocity are accumulated in the nanoscopic device and the electric property deteriorates. We estimate the relaxation time of the LO phonon and investigate its dependency on the oxide thickness. The calculation results show that the LO phonon decays faster as the oxide thickness increases and turns into acoustic phonon. The result indicates that the presence of SiO2 films promotes the scattering of the phonon and this is effective to diminish the optical phonon.","PeriodicalId":331098,"journal":{"name":"2010 International Conference on Simulation of Semiconductor Processes and Devices","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121199178","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A Kinetic Monte Carlo study on the dynamic switching properties of electrochemical metallization RRAMs during the SET process 电化学金属化rram在SET过程中动态开关特性的动力学蒙特卡罗研究
2010 International Conference on Simulation of Semiconductor Processes and Devices Pub Date : 2010-10-14 DOI: 10.1109/SISPAD.2010.5604584
Feng Pan, V. Subramanian
{"title":"A Kinetic Monte Carlo study on the dynamic switching properties of electrochemical metallization RRAMs during the SET process","authors":"Feng Pan, V. Subramanian","doi":"10.1109/SISPAD.2010.5604584","DOIUrl":"https://doi.org/10.1109/SISPAD.2010.5604584","url":null,"abstract":"In this paper, a simulation process based on Kinetic Monte Carlo (KMC) for an electrochemical metallization (ECM) resistive RAM (RRAM) is demonstrated. This simulation tool can investigate all the major dynamics properties of such devices. In particular, the voltage sweep rate dependent I–V characteristics, the variations of SET voltage, writing speed, on-state resistance, filament overgrowth phenomena and the effect of material properties are studied.","PeriodicalId":331098,"journal":{"name":"2010 International Conference on Simulation of Semiconductor Processes and Devices","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125360836","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
Future high density memories for computing applications: Device behavior and modeling challenges 未来用于计算应用的高密度存储器:设备行为和建模挑战
2010 International Conference on Simulation of Semiconductor Processes and Devices Pub Date : 2010-10-14 DOI: 10.1109/SISPAD.2010.5604521
G. Spadini, I. Karpov, D. Kencke
{"title":"Future high density memories for computing applications: Device behavior and modeling challenges","authors":"G. Spadini, I. Karpov, D. Kencke","doi":"10.1109/SISPAD.2010.5604521","DOIUrl":"https://doi.org/10.1109/SISPAD.2010.5604521","url":null,"abstract":"Memory elements existing and under research are compared for their suitability in computer memory applications. Cross point arrays of phase change elements with matched isolation devices are found to be particularly attractive and the challenge to model them is analyzed.","PeriodicalId":331098,"journal":{"name":"2010 International Conference on Simulation of Semiconductor Processes and Devices","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122104622","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Lithography induced layout variations in 6-T SRAM cells 光刻诱导6-T SRAM细胞的布局变化
2010 International Conference on Simulation of Semiconductor Processes and Devices Pub Date : 2010-10-14 DOI: 10.1109/SISPAD.2010.5604543
C. Kampen, P. Evanschitzky, A. Burenkov, J. Lorenz
{"title":"Lithography induced layout variations in 6-T SRAM cells","authors":"C. Kampen, P. Evanschitzky, A. Burenkov, J. Lorenz","doi":"10.1109/SISPAD.2010.5604543","DOIUrl":"https://doi.org/10.1109/SISPAD.2010.5604543","url":null,"abstract":"A simulation study of lithography induced layout variations in 6-T SRAM cells is presented. Lithography simulations of a complete 6-T SRAM cell layout, including active n+/p+ regions layer and poly-gate layer were performed. The smallest feature size was assumed to be 45 nm. 76 positions of the projector focus were simulated for each layer in total. TCAD simulations of 32nm single gate FD SOI MOSFETs were performed to calculate the electrical behavior. SPICE parameters were extracted from reference results obtained by TCAD simulations. More than 5000 variations of the the static and dynamic SRAM cell performance in dependence on lithography induced variations of the physical transistor width and the physical gate length were simulated.","PeriodicalId":331098,"journal":{"name":"2010 International Conference on Simulation of Semiconductor Processes and Devices","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124979539","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Impact of parameter variability on electromigration lifetime distribution 参数变异性对电迁移寿命分布的影响
2010 International Conference on Simulation of Semiconductor Processes and Devices Pub Date : 2010-10-14 DOI: 10.1109/SISPAD.2010.5604523
H. Ceric, R. L. de Orio, S. Selberherr
{"title":"Impact of parameter variability on electromigration lifetime distribution","authors":"H. Ceric, R. L. de Orio, S. Selberherr","doi":"10.1109/SISPAD.2010.5604523","DOIUrl":"https://doi.org/10.1109/SISPAD.2010.5604523","url":null,"abstract":"The interconnect scaling and the introduction of new processes and materials raise an issue of justifiability and applicability of phenomenological continuum-level models. The parameters of continuum-level electromigration models are averages over values which generally vary on microscopic and atomistic scale. Therefore it is necessary to investigate under which conditions these microscopic or atomistic spatial variations influence the validity of continuum models. Regarding both important parameters of continuum-level electromigration models, effective valence Z* and vacancy diffusivity, their variations depend on crystal orientation and the variations between bulk, grain boundaries, and interfaces. We apply the results of quantum mechanical calculations of the effective valence in order to parameterize the continuum electromigration model and subsequently investigate the impact of parameter variation on the variability of the electromigration behavior.","PeriodicalId":331098,"journal":{"name":"2010 International Conference on Simulation of Semiconductor Processes and Devices","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117333959","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Numerical investigation of the total SOA of trench field-plate LDMOS devices 沟槽场板LDMOS器件总SOA的数值研究
2010 International Conference on Simulation of Semiconductor Processes and Devices Pub Date : 2010-10-14 DOI: 10.1109/SISPAD.2010.5604555
S. Poli, S. Reggiani, G. Baccarani, E. Gnani, A. Gnudi, M. Denison, S. Pendharkar, R. Wise
{"title":"Numerical investigation of the total SOA of trench field-plate LDMOS devices","authors":"S. Poli, S. Reggiani, G. Baccarani, E. Gnani, A. Gnudi, M. Denison, S. Pendharkar, R. Wise","doi":"10.1109/SISPAD.2010.5604555","DOIUrl":"https://doi.org/10.1109/SISPAD.2010.5604555","url":null,"abstract":"A numerical investigation of electrical and thermal properties of a lateral trench field-plate (TFP) LDMOS is proposed. Beside the advantage in terms of specific on-resistance (RSP) vs. breakdown voltage (VBD) trade-off, achieved with a proper optimization of the geometrical and doping parameters, the use of deep trenches is discussed here with particular attention to their impact on the electrical safe-operating area (SOA), hot-carrier stress (HCS) reliability, self-heating effects (SHE) and thermal SOA.","PeriodicalId":331098,"journal":{"name":"2010 International Conference on Simulation of Semiconductor Processes and Devices","volume":"13 2","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132434159","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
A theoretical study of effect of gate voltage on electron-modulated-acoustic-phonon interactions in silicon nanowire MOSFETs 栅极电压对硅纳米线mosfet中电子调制声声子相互作用影响的理论研究
2010 International Conference on Simulation of Semiconductor Processes and Devices Pub Date : 2010-10-14 DOI: 10.1109/SISPAD.2010.5604562
J. Hattori, S. Uno, N. Mori, K. Nakazato
{"title":"A theoretical study of effect of gate voltage on electron-modulated-acoustic-phonon interactions in silicon nanowire MOSFETs","authors":"J. Hattori, S. Uno, N. Mori, K. Nakazato","doi":"10.1109/SISPAD.2010.5604562","DOIUrl":"https://doi.org/10.1109/SISPAD.2010.5604562","url":null,"abstract":"We theoretically investigate the gate voltage dependence of the interaction between modulated acoustic phonons and electrons in SiO2-coated Si nanowires. The gate voltage decreases the form factor calculated with modulated acoustic phonons as well as that for bulk phonons. However, the relative difference between the two form factors, that is, the phonon modulation effect on the form factor becomes larger with increasing gate voltage. In addition, we evaluate the phonon modulation effect on the electron mobility in the Si nanowires, and reveal that the effect becomes smaller with increasing gate voltage.","PeriodicalId":331098,"journal":{"name":"2010 International Conference on Simulation of Semiconductor Processes and Devices","volume":"285 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133107594","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
FinFET SRAM cell optimization considering temporal variability due to NBTI/PBTI and surface orientation 考虑NBTI/PBTI和表面取向引起的时间变化的FinFET SRAM单元优化
2010 International Conference on Simulation of Semiconductor Processes and Devices Pub Date : 2010-10-14 DOI: 10.1109/SISPAD.2010.5604510
V. Hu, M. Fan, Chien-Yu Hsieh, P. Su, C. Chuang
{"title":"FinFET SRAM cell optimization considering temporal variability due to NBTI/PBTI and surface orientation","authors":"V. Hu, M. Fan, Chien-Yu Hsieh, P. Su, C. Chuang","doi":"10.1109/SISPAD.2010.5604510","DOIUrl":"https://doi.org/10.1109/SISPAD.2010.5604510","url":null,"abstract":"This paper analyzes the impact of intrinsic process variation and NBTI/PBTI induced time-dependent variations on the stability/variability of 6T FinFET SRAM cells with various surface orientations. Due to quantum confinement, (110)-oriented pull-down devices with fin Line Edge Roughness (LER) show larger Vread,0 and Vtrip variations, thus degrading RSNM and its variability. (100)-oriented pull-up devices with fin LER show larger Vwrite,0 and Vtrip variations, hence degrade the variability of WSNM. The combined effects of intrinsic process variation and NBTI/PBTI induced variations have been examined to optimize the FinFET SRAM cells. Pull-up devices with (110) orientation suffer larger NBTI, resulting in large Vtrip variation and significant degradation of RSNM. Our study indicates that consideration of NBTI/PBTI induced temporal variation changes the optimal choice of FinFET SRAM cell surface orientations in term of μRSNM/σRSNM.","PeriodicalId":331098,"journal":{"name":"2010 International Conference on Simulation of Semiconductor Processes and Devices","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123291603","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Halo profile engineering to reduce Vt fluctuation in high-k/metal-gate nMOSFET 高k/金属栅极nMOSFET中减小Vt波动的光晕轮廓工程
2010 International Conference on Simulation of Semiconductor Processes and Devices Pub Date : 2010-10-14 DOI: 10.1109/SISPAD.2010.5604546
W.-Y. Chen, T. Yu, T. Ohtou, Y. Sheu, Jeff Wu, Cheewee Liu
{"title":"Halo profile engineering to reduce Vt fluctuation in high-k/metal-gate nMOSFET","authors":"W.-Y. Chen, T. Yu, T. Ohtou, Y. Sheu, Jeff Wu, Cheewee Liu","doi":"10.1109/SISPAD.2010.5604546","DOIUrl":"https://doi.org/10.1109/SISPAD.2010.5604546","url":null,"abstract":"In this work, new halo profile engineering is proposed to suppress the threshold voltage variation (σVt) caused by discrete random dopant fluctuation (RDF). An in-house 3D atomistic numerical simulation tool is utilized to assess nMOSFETs σVt caused by RDF for a HK/MG process. The results show that σVt can be effectively suppressed by 10% by optimizing rotation and tilt angles of the halo implant.","PeriodicalId":331098,"journal":{"name":"2010 International Conference on Simulation of Semiconductor Processes and Devices","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124268358","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Schrödinger-Poisson and Monte Carlo analysis of III–V MOSFETs for high frequency and low consumption applications Schrödinger-Poisson和蒙特卡罗分析III-V型mosfet的高频和低功耗应用
2010 International Conference on Simulation of Semiconductor Processes and Devices Pub Date : 2010-10-14 DOI: 10.1109/SISPAD.2010.5604563
Ming Shi, J. Saint-Martin, A. Bournel, P. Dollfus
{"title":"Schrödinger-Poisson and Monte Carlo analysis of III–V MOSFETs for high frequency and low consumption applications","authors":"Ming Shi, J. Saint-Martin, A. Bournel, P. Dollfus","doi":"10.1109/SISPAD.2010.5604563","DOIUrl":"https://doi.org/10.1109/SISPAD.2010.5604563","url":null,"abstract":"III–V MOSFET (Metal Oxide Semiconductor Field Effect Transistor) with high-κ gate dielectric stack appears as a viable alternative to enhance not only microwave performance but also logic circuits with low supply voltage. This allows fulfilling high-speed and low-power specifications for intelligent applications. Indeed, combining weak gate leakage of standard MOSFETs and good RF performance of HEMTs (High Electron Mobility Transistors), they could outperform end-of-roadmap standard Si-MOSFET. Using full 2D Poisson-Schrödinger solver and a semi-classical Ensemble Monte Carlo device simulator, various 50nm MOSFET and HEMT are investigated in terms of gate charge control and both static and dynamic I–V performance. In particular, Y parameters are carefully extracted from time-varying currents. This comparative study allows us to propose an optimized III–V nano-FET architecture with high-frequency performance under low power supply.","PeriodicalId":331098,"journal":{"name":"2010 International Conference on Simulation of Semiconductor Processes and Devices","volume":"86 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122622624","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
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