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2010 International Conference on Simulation of Semiconductor Processes and Devices最新文献

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Three-dimensional simulation of focused ion beam processing using the level set method 用水平集方法模拟聚焦离子束加工的三维过程
2010 International Conference on Simulation of Semiconductor Processes and Devices Pub Date : 2010-10-14 DOI: 10.1109/SISPAD.2010.5604573
O. Ertl, L. Filipovic, S. Selberherr
{"title":"Three-dimensional simulation of focused ion beam processing using the level set method","authors":"O. Ertl, L. Filipovic, S. Selberherr","doi":"10.1109/SISPAD.2010.5604573","DOIUrl":"https://doi.org/10.1109/SISPAD.2010.5604573","url":null,"abstract":"Three-dimensional simulations of focused ion beam milling, which use the level set method for surface evolution, are presented for the first time. This approach allows the inherent description of topological changes. The surface rates are calculated using Monte Carlo ray tracing in order to incorporate shadowing as well as redeposition. Parallelization is used to reduce the computation time.","PeriodicalId":331098,"journal":{"name":"2010 International Conference on Simulation of Semiconductor Processes and Devices","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129143849","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Compact process and layout aware model for variability optimization of circuit in nanoscale CMOS 纳米级CMOS电路变异性优化的紧凑工艺和布局感知模型
2010 International Conference on Simulation of Semiconductor Processes and Devices Pub Date : 2010-10-14 DOI: 10.1109/SISPAD.2010.5604545
Yohan Kim, Jong-Wook Jeon, Yong-Un Jang, Yonghee Park, Gi-Young Yang, Young-Kwan Park, Moon-Hyun Yoo, C. Chung
{"title":"Compact process and layout aware model for variability optimization of circuit in nanoscale CMOS","authors":"Yohan Kim, Jong-Wook Jeon, Yong-Un Jang, Yonghee Park, Gi-Young Yang, Young-Kwan Park, Moon-Hyun Yoo, C. Chung","doi":"10.1109/SISPAD.2010.5604545","DOIUrl":"https://doi.org/10.1109/SISPAD.2010.5604545","url":null,"abstract":"A predictive MOSFET model is very critical for early circuit design in nanoscale CMOS technologies. In this work, we developed a new compact MOSFET model which can dramatically improve the predictability of BSIM4 for the major 3 process and 2 layout variations by applying the simple physics-based equations to model these parameters. The accuracy of the model is verified using numerical TCAD simulation results and measurements under full range of temperature and bias conditions. The compact model for the circuit simulation can be efficiently used to predict the effects of process and layout variations on the circuit characteristics.","PeriodicalId":331098,"journal":{"name":"2010 International Conference on Simulation of Semiconductor Processes and Devices","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116270846","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A novel algorithm for the solution of charge transport equations in MANOS devices including charge trapping in alumina and temperature effects 一种求解MANOS器件中电荷输运方程的新算法，包括氧化铝中的电荷捕获和温度效应
2010 International Conference on Simulation of Semiconductor Processes and Devices Pub Date : 2010-10-14 DOI: 10.1109/SISPAD.2010.5604519
A. Padovani, L. Larcher
{"title":"A novel algorithm for the solution of charge transport equations in MANOS devices including charge trapping in alumina and temperature effects","authors":"A. Padovani, L. Larcher","doi":"10.1109/SISPAD.2010.5604519","DOIUrl":"https://doi.org/10.1109/SISPAD.2010.5604519","url":null,"abstract":"We present a new algorithm for the exact solution of the system of equations describing charge trapping and transport across the dielectric stack of nitride-based charge trapping memories. The algorithm is implemented in a physical MANOS model accounting for temperature effects and charge trapping into the Al2O3 blocking layer. The model reproduces threshold voltage shifts measured at different temperatures on different MANOS stacks.","PeriodicalId":331098,"journal":{"name":"2010 International Conference on Simulation of Semiconductor Processes and Devices","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122581941","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Transport and noise properties of graphene-based transistors revealed through atomistic modelling 通过原子模型揭示石墨烯基晶体管的输运和噪声特性
2010 International Conference on Simulation of Semiconductor Processes and Devices Pub Date : 2010-10-14 DOI: 10.1109/SISPAD.2010.5604587
G. Iannaccone, A. Betti, G. Fiori
{"title":"Transport and noise properties of graphene-based transistors revealed through atomistic modelling","authors":"G. Iannaccone, A. Betti, G. Fiori","doi":"10.1109/SISPAD.2010.5604587","DOIUrl":"https://doi.org/10.1109/SISPAD.2010.5604587","url":null,"abstract":"We discuss an intriguing set of transport and noise properties of graphene-based transistors that can be investigated in a direct way with atomistic modeling - Non-Equilibrium Green's Functions with a Tight-Binding Hamiltonian - and are not directly accessible with models based on a higher level of physical abstraction. We present an investigation of the achievable electron mobility in channels based on graphene nanoribbons with realistic imperfections. Then, we will discuss how the small gap and small density of states of bilayer graphene can be used to design tunnel FETs with extremely steep subthreshold slope. Then, as far as noise is concerned, we will show the impact of electron-electron interaction and of interband transitions in enhancing the channel noise of FETs based on small-gap carbon nanotubes.","PeriodicalId":331098,"journal":{"name":"2010 International Conference on Simulation of Semiconductor Processes and Devices","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127467779","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Compact modeling of Fe-FET and implications on variation-insensitive design Fe-FET的紧凑建模及其对变化不敏感设计的启示
2010 International Conference on Simulation of Semiconductor Processes and Devices Pub Date : 2010-10-14 DOI: 10.1109/SISPAD.2010.5604516
Chi-Chao Wang, Y. Ye, Yu Cao
{"title":"Compact modeling of Fe-FET and implications on variation-insensitive design","authors":"Chi-Chao Wang, Y. Ye, Yu Cao","doi":"10.1109/SISPAD.2010.5604516","DOIUrl":"https://doi.org/10.1109/SISPAD.2010.5604516","url":null,"abstract":"Semiconductor devices with self-feedback mechanisms are considered as a promising alternative to traditional CMOS, in order to achieve faster operation and lower switching energy. Examples include IMOS and FBFET that are operated in a non-equilibrium condition to rapidly generate mobile carriers [1–2]. More recently, Fe-FET was proposed to improve the switching by integrating a ferroelectric material as gate insulator in a MOSFET structure [3–5]. Under particular circumstance, ferroelectric capacitance is effectively negative, due to the negative slope of its polarization-electrical field (P-E) curve. This property makes the ferroelectric layer a voltage amplifier to boost surface potential, achieving fast transition. In this paper: (1) A new threshold voltage model is developed to capture the feedback of negative capacitance and IV characteristics of Fe-FET; (2) It is further revealed that the impact of random dopant fluctuation (RDF) on leakage variability can be significantly suppressed in Fe-FET, by tuning the thickness of the ferroelectric layer.","PeriodicalId":331098,"journal":{"name":"2010 International Conference on Simulation of Semiconductor Processes and Devices","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115347901","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
Strain effects on hole current in silicon nanowire FETs 应变对硅纳米线场效应管空穴电流的影响
2010 International Conference on Simulation of Semiconductor Processes and Devices Pub Date : 2010-10-14 DOI: 10.1109/SISPAD.2010.5604528
H. Minari, T. Kitayama, Masahiro Yamamoto, N. Mori
{"title":"Strain effects on hole current in silicon nanowire FETs","authors":"H. Minari, T. Kitayama, Masahiro Yamamoto, N. Mori","doi":"10.1109/SISPAD.2010.5604528","DOIUrl":"https://doi.org/10.1109/SISPAD.2010.5604528","url":null,"abstract":"Hole transport simulation based on the nonequilibrium Green's function and tight-binding formalism has been performed for strained Si nanowire FETs with a diameter of 1.5nm and 2.5 nm. Simulation results show that for Si nanowire FETs with a diameter of 2.5 nm, the compressive strain enhances the ballistic hole current, while the tensile strain gives opposite results. For Si nanowire FETs with a diameter of 1.5 nm, the ballistic hole current hardly depends on the strain magnitude.","PeriodicalId":331098,"journal":{"name":"2010 International Conference on Simulation of Semiconductor Processes and Devices","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123894038","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Analytical models of effective DOS, saturation velocity and high-field mobility for SiGe HBTs numerical simulation SiGe HBTs数值模拟的有效DOS、饱和速度和高场迁移率分析模型
2010 International Conference on Simulation of Semiconductor Processes and Devices Pub Date : 2010-10-14 DOI: 10.1109/SISPAD.2010.5604505
G. Sasso, N. Rinaldi, G. Matz, C. Jungemann
{"title":"Analytical models of effective DOS, saturation velocity and high-field mobility for SiGe HBTs numerical simulation","authors":"G. Sasso, N. Rinaldi, G. Matz, C. Jungemann","doi":"10.1109/SISPAD.2010.5604505","DOIUrl":"https://doi.org/10.1109/SISPAD.2010.5604505","url":null,"abstract":"Effective density of state, saturation velocity and high field mobility analytical models for hydrodynamic simulation of silicon-germanium hetero-junction bipolar transistors have been derived.","PeriodicalId":331098,"journal":{"name":"2010 International Conference on Simulation of Semiconductor Processes and Devices","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128082350","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 17
Symmetry reduction by surface scattering and mobility model for stressed 〈100〉/(001) MOSFETs 应力< 100 > /(001)mosfet的表面散射对称性降低和迁移率模型
2010 International Conference on Simulation of Semiconductor Processes and Devices Pub Date : 2010-10-14 DOI: 10.1109/SISPAD.2010.5604508
F. M. Bufler, A. Erlebach, M. Oulmane
{"title":"Symmetry reduction by surface scattering and mobility model for stressed 〈100〉/(001) MOSFETs","authors":"F. M. Bufler, A. Erlebach, M. Oulmane","doi":"10.1109/SISPAD.2010.5604508","DOIUrl":"https://doi.org/10.1109/SISPAD.2010.5604508","url":null,"abstract":"It is demonstrated that the gate interface breaks the equivalence between vertical and transverse direction for the mobility in 〈100〉/(001) pMOSFETs, leading to 6 instead of 3 independent 1st order piezoconductance coefficients. This is found from Monte Carlo (MC) simulations yielding different effective mobilities for uniaxial vertical and transverse stress, which can be explained in terms of energy and parallel-momentum conservation upon specular surface scattering. A mobility model with stress-dependent 1st order piezoconductance coefficients is presented. This model is shown to reproduce well corresponding MC effective mobilities not only for low, but also for high stress.","PeriodicalId":331098,"journal":{"name":"2010 International Conference on Simulation of Semiconductor Processes and Devices","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131425175","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
A comparative 3D simulation approach with extensive experimental Vt/Avt data and analysis of LER/RDF/reliability of CMOS SRAMs at 40-nm node and beyond 基于大量实验Vt/Avt数据的对比三维仿真方法，以及40nm及以上节点CMOS sram的LER/RDF/可靠性分析
2010 International Conference on Simulation of Semiconductor Processes and Devices Pub Date : 2010-10-14 DOI: 10.1109/SISPAD.2010.5604551
T. Okada, H. Yoshimura, H. Aikawa, M. Sengoku, O. Fujii, H. Oyamatsu
{"title":"A comparative 3D simulation approach with extensive experimental Vt/Avt data and analysis of LER/RDF/reliability of CMOS SRAMs at 40-nm node and beyond","authors":"T. Okada, H. Yoshimura, H. Aikawa, M. Sengoku, O. Fujii, H. Oyamatsu","doi":"10.1109/SISPAD.2010.5604551","DOIUrl":"https://doi.org/10.1109/SISPAD.2010.5604551","url":null,"abstract":"With the advent of CMOS SRAMs manufactured at 40-nm node and beyond, variability of threshold voltage (Vt) and technology-dependent factor in Pelgrom plot (Avt) has become a serious issue in the practical design and fabrication phases. This paper presents (i) a comparative 3D simulation approach using extensive measured data to clarify the magnitudes of LER and RDF effects in generic processes, (ii) estimation of magnitudes of LER, RDF and FER (metallurgical junction front edge roughness) effects, (iii) simulation of LER, RDF and FER in a FinFET device to evaluate practical feasibility and (iv) analysis of size-dependent NBTI-induced Vt fluctuation as a possible application of this method.","PeriodicalId":331098,"journal":{"name":"2010 International Conference on Simulation of Semiconductor Processes and Devices","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129963358","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Modeling of 2D bias control in overlap region of high-voltage MOSFETs for accurate device/circuit performance prediction 高压mosfet重叠区的二维偏置控制建模，以实现精确的器件/电路性能预测
2010 International Conference on Simulation of Semiconductor Processes and Devices Pub Date : 2010-10-14 DOI: 10.1109/SISPAD.2010.5604515
A. Tanaka, Y. Oritsuki, H. Kikuchihara, M. Miyake, H. Mattausch, M. Miura-Mattausch, Y. Liu, K. Green
{"title":"Modeling of 2D bias control in overlap region of high-voltage MOSFETs for accurate device/circuit performance prediction","authors":"A. Tanaka, Y. Oritsuki, H. Kikuchihara, M. Miyake, H. Mattausch, M. Miura-Mattausch, Y. Liu, K. Green","doi":"10.1109/SISPAD.2010.5604515","DOIUrl":"https://doi.org/10.1109/SISPAD.2010.5604515","url":null,"abstract":"High-voltage MOSFETs enable wide biasrange applications realized only by optimizing the device structure. We have developed the compact model HiSIM_HV 2.0.0, based on the potential distribution in the device, which is useful for both device and circuit optimizations. By considering two device-structure dependent potentials, the internal node potential within the high resistive drift region and the potential underneath the gate overlap region, the model can reproduce I–V characteristics for a wide range of structure variations without additional fitting parameters.","PeriodicalId":331098,"journal":{"name":"2010 International Conference on Simulation of Semiconductor Processes and Devices","volume":"238 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132090086","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
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