基于大量实验Vt/Avt数据的对比三维仿真方法，以及40nm及以上节点CMOS sram的LER/RDF/可靠性分析

2010 International Conference on Simulation of Semiconductor Processes and Devices Pub Date : 2010-10-14 DOI:10.1109/SISPAD.2010.5604551

T. Okada, H. Yoshimura, H. Aikawa, M. Sengoku, O. Fujii, H. Oyamatsu

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引用次数: 0

摘要

随着40纳米及以上节点CMOS sram的出现，阈值电压(Vt)的可变性和Pelgrom图(Avt)的技术依赖因素已成为实际设计和制造阶段的一个严重问题。本文提出了(i)一种使用大量测量数据的比较三维模拟方法，以阐明一般过程中LER、RDF和FER(冶金结前缘粗糙度)效应的大小，(ii)估计LER、RDF和FER(冶金结前缘粗糙度)效应的大小，(iii)在FinFET器件中模拟LER、RDF和FER以评估实际可行性，以及(iv)分析该方法可能应用的nbti诱导的尺寸依赖性Vt波动。

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A comparative 3D simulation approach with extensive experimental Vt/Avt data and analysis of LER/RDF/reliability of CMOS SRAMs at 40-nm node and beyond

With the advent of CMOS SRAMs manufactured at 40-nm node and beyond, variability of threshold voltage (Vt) and technology-dependent factor in Pelgrom plot (Avt) has become a serious issue in the practical design and fabrication phases. This paper presents (i) a comparative 3D simulation approach using extensive measured data to clarify the magnitudes of LER and RDF effects in generic processes, (ii) estimation of magnitudes of LER, RDF and FER (metallurgical junction front edge roughness) effects, (iii) simulation of LER, RDF and FER in a FinFET device to evaluate practical feasibility and (iv) analysis of size-dependent NBTI-induced Vt fluctuation as a possible application of this method.

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2010 International Conference on Simulation of Semiconductor Processes and Devices

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