Halo profile engineering to reduce Vt fluctuation in high-k/metal-gate nMOSFET

Abstract

In this work, new halo profile engineering is proposed to suppress the threshold voltage variation (σVt) caused by discrete random dopant fluctuation (RDF). An in-house 3D atomistic numerical simulation tool is utilized to assess nMOSFETs σVt caused by RDF for a HK/MG process. The results show that σVt can be effectively suppressed by 10% by optimizing rotation and tilt angles of the halo implant.