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System matrix compression for spherical harmonics expansions of the Boltzmann transport equation 玻尔兹曼输运方程球面谐波展开的系统矩阵压缩
2010 International Conference on Simulation of Semiconductor Processes and Devices Pub Date : 2010-10-14 DOI: 10.1109/SISPAD.2010.5604542
K. Rupp, T. Grasser, A. Jungel
{"title":"System matrix compression for spherical harmonics expansions of the Boltzmann transport equation","authors":"K. Rupp, T. Grasser, A. Jungel","doi":"10.1109/SISPAD.2010.5604542","DOIUrl":"https://doi.org/10.1109/SISPAD.2010.5604542","url":null,"abstract":"Due to its deterministic nature, the spherical harmonics expansion of the Boltzmann transport equation is an attractive alternative to the Monte Carlo method for the purpose of electronic device simulation. The major drawback when using higher order expansions is the huge memory requirement, especially for two- and three-dimensional simulations. We propose a method to compress the resulting system of linear equations, such that memory requirements are reduced by up to two orders of magnitude. In that context we discuss criteria for the selection of an appropriate linear equation solver and show that execution times for matrix-vector multiplications using the compressed matrix scheme on a single CPU core are comparable to that of an uncompressed system matrix. Numerical results demonstrate the applicability of our method and confirm our theoretical results.","PeriodicalId":331098,"journal":{"name":"2010 International Conference on Simulation of Semiconductor Processes and Devices","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129699372","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Simulation of three dimensional grain growth for Cu-interconnects cu互连线三维晶粒生长模拟
2010 International Conference on Simulation of Semiconductor Processes and Devices Pub Date : 2010-10-14 DOI: 10.1109/SISPAD.2010.5604581
Xiaoxu Cheng, Yan Wang
{"title":"Simulation of three dimensional grain growth for Cu-interconnects","authors":"Xiaoxu Cheng, Yan Wang","doi":"10.1109/SISPAD.2010.5604581","DOIUrl":"https://doi.org/10.1109/SISPAD.2010.5604581","url":null,"abstract":"The temporal evolution and morphology of three-dimensional (3-D) grain growth in Cu interconnect are simulated by phase-field model techniques. In the simulation, a new local free energy density function is proposed in which the field variables can be reduced from 200 to 20. By restraining the grain orientations in the side face of interconnect, the model is applicable to simulating the microstructure evolution of polycrystalline Cu-lines in addition to the conventional 2-D or 3-D grain topology. The dependence of grain size on the line width is analyzed systematically. With the obtained topology of Cu grains and morphology of the line boundary, the resistivity of Cu interconnects is estimated by conventional Monte Carlo simulation which are tested with different experimental data. These results are important for evaluation and optimization the Cu interconnect process.","PeriodicalId":331098,"journal":{"name":"2010 International Conference on Simulation of Semiconductor Processes and Devices","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128560609","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Modeling gate-pitch scaling impact on stress-induced mobility and external resistance for 20nm-node MOSFETs 栅极-节距缩放对20nm节点mosfet应力诱导迁移率和外部电阻影响的建模
2010 International Conference on Simulation of Semiconductor Processes and Devices Pub Date : 2010-10-14 DOI: 10.1109/SISPAD.2010.5604566
Seong-Dong Kim, Sameer H. Jain, H. Rhee, A. Scholze, M. Yu., S. Lee, S. Furkay, M. Zorzi, F. M. Bufler, A. Erlebach
{"title":"Modeling gate-pitch scaling impact on stress-induced mobility and external resistance for 20nm-node MOSFETs","authors":"Seong-Dong Kim, Sameer H. Jain, H. Rhee, A. Scholze, M. Yu., S. Lee, S. Furkay, M. Zorzi, F. M. Bufler, A. Erlebach","doi":"10.1109/SISPAD.2010.5604566","DOIUrl":"https://doi.org/10.1109/SISPAD.2010.5604566","url":null,"abstract":"The impact of gate-pitch scaling on device internal and external resistance is examined by advanced process and device modeling including distributed contact resistance model, mechanical stress and Monte Carlo (MC)-based stress-dependent mobility model. The contact resistance components and their major parameters in sub-50nm contact regime are analyzed by TCAD and transmission line modeling (TLM). The calibration method for the stress-induced channel mobility and the external resistance is proposed using Ron-Lgate measurements of 32nm-node devices with different gate-pitches. The significant performance degradation due to simple gate-pitch scaling is predicted for 20nm-node technology with sub-100nm gate-pitch.","PeriodicalId":331098,"journal":{"name":"2010 International Conference on Simulation of Semiconductor Processes and Devices","volume":"71 4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130383661","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Multiphysics modeling of PCM devices for scaling investigation 用于标度研究的PCM器件多物理场建模
2010 International Conference on Simulation of Semiconductor Processes and Devices Pub Date : 2010-10-14 DOI: 10.1109/SISPAD.2010.5604509
G. Ferrari, A. Ghetti, D. Ielmini, A. Redaelli, A. Pirovano
{"title":"Multiphysics modeling of PCM devices for scaling investigation","authors":"G. Ferrari, A. Ghetti, D. Ielmini, A. Redaelli, A. Pirovano","doi":"10.1109/SISPAD.2010.5604509","DOIUrl":"https://doi.org/10.1109/SISPAD.2010.5604509","url":null,"abstract":"A multiphysics model for Phase Change Memory (PCM) is calibrated on a large set of experimental data. Critical material and interface properties such as electrical and thermal resistivities and their dependence on temperature are extracted from data or fitting electrical characteristics with numerical simulations. The model is shown to match with a unique set of parameters experimental data from 90nm and 45nm technology nodes. The calibrated model is then exploited to perform a sensitivity analysis of key cell characteristics to geometry and material properties variations. Furthermore, the model is used to predict performance of a scaled down cell suitable for the 32nm technology node and the results demonstrate the consistent scalability of PCM with respect to the technology node.","PeriodicalId":331098,"journal":{"name":"2010 International Conference on Simulation of Semiconductor Processes and Devices","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132088889","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
Modeling and fast simulation of RF-MEMS switches within standard IC design frameworks RF-MEMS开关在标准IC设计框架内的建模和快速仿真
2010 International Conference on Simulation of Semiconductor Processes and Devices Pub Date : 2010-10-14 DOI: 10.1109/SISPAD.2010.5604496
M. Niessner, G. Schrag, G. Wachutka, J. Iannacci
{"title":"Modeling and fast simulation of RF-MEMS switches within standard IC design frameworks","authors":"M. Niessner, G. Schrag, G. Wachutka, J. Iannacci","doi":"10.1109/SISPAD.2010.5604496","DOIUrl":"https://doi.org/10.1109/SISPAD.2010.5604496","url":null,"abstract":"We present a macromodel of an electrostatically actuated and viscously damped ohmic contact RF-MEMS switch suitable for direct implementation in standard IC design frameworks. The physics-based and multi-energy domain coupled model is systematically derived on the basis of a hierarchical modeling approach. The very good agreement with measurements proves the capability of the model to predict the behavior of the RF-MEMS switch. Especially effects due to the nonlinear coupling of the different energy domains are correctly reproduced. The accurate reproduction of heavily contact-related situations within acceptable computing time is identified as an issue for future research.","PeriodicalId":331098,"journal":{"name":"2010 International Conference on Simulation of Semiconductor Processes and Devices","volume":"121 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127609801","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
Improving channel mobility in graphene-FETs by minimizing surface phonon scattering - A simulation study 通过最小化表面声子散射提高石墨烯-场效应管沟道迁移率-模拟研究
2010 International Conference on Simulation of Semiconductor Processes and Devices Pub Date : 2010-10-14 DOI: 10.1109/SISPAD.2010.5604586
Xinxin Yu, Jiahao Kang, Jinyu Zhang, L. Tian, Zhiping Yu
{"title":"Improving channel mobility in graphene-FETs by minimizing surface phonon scattering - A simulation study","authors":"Xinxin Yu, Jiahao Kang, Jinyu Zhang, L. Tian, Zhiping Yu","doi":"10.1109/SISPAD.2010.5604586","DOIUrl":"https://doi.org/10.1109/SISPAD.2010.5604586","url":null,"abstract":"In graphene-based field-effect transistors (graphene FETs), the carrier channel mobility is strongly influenced by substrate and gate dielectric materials. In this paper, we theoretically investigated the carrier channel mobility for the graphene-FET. Surface phonon (SP) scattering, screened Coulomb scattering, acoustic phonon and optical phonon scattering mechanisms are considered in the mobility calculation. Applying Mahan's theory, the SP scattering in a gate stack structure is evaluated. It is found that SP scattering plays an important role especially in high-k dielectrics. The charged impurity and SP scattering can be suppressed effectively by inserting a polymer layer between the gate dielectric and graphene. The thickness of the ploymer layer, however, should be carefully selected to balance the channel carrier mobility enhancement and gate control ability. Our calculation results are consistent with previous calculations and experimental observations.","PeriodicalId":331098,"journal":{"name":"2010 International Conference on Simulation of Semiconductor Processes and Devices","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134162812","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Investigation of charge loss mechanisms in planar and raised STI charge trapping flash memories 平面和凸起STI电荷捕获快闪记忆体中电荷损失机制的研究
2010 International Conference on Simulation of Semiconductor Processes and Devices Pub Date : 2010-10-14 DOI: 10.1109/SISPAD.2010.5604520
Z. Xia, Dae Sin Kim, Ju-Yul Lee, Keun-Ho Lee, Young-Kwan Park, Moon-Hyun Yoo, C. Chung
{"title":"Investigation of charge loss mechanisms in planar and raised STI charge trapping flash memories","authors":"Z. Xia, Dae Sin Kim, Ju-Yul Lee, Keun-Ho Lee, Young-Kwan Park, Moon-Hyun Yoo, C. Chung","doi":"10.1109/SISPAD.2010.5604520","DOIUrl":"https://doi.org/10.1109/SISPAD.2010.5604520","url":null,"abstract":"A comprehensive simulation to investigate the charge loss mechanisms in planar and raised STI NAND-type charge trapping flash (CTF) memories with careful calibrations is present. The tunneling and silicon nitride trap transport with Poole-Frenkel (PF) effect are solved self-consistently and validated based on the experimental data including gate stacks leakage, program speed, and high temperature retention. Based on the programmed state, the high temperature retention is simulated and compared with the measurement data. In planar CTF, the vertical charge loss through tunneling layers and blocking layers are analyzed. The results show that the former is the dominant one. Finally, the charge loss in raised STI CTF is compared with that in planar CTF. The results show that the enhanced charge loss in raised STI CTF is induced by the lateral spreading and the non-uniform charge storage nearby the STI edge, especially in the narrow width (100nm) raised STI CTF.","PeriodicalId":331098,"journal":{"name":"2010 International Conference on Simulation of Semiconductor Processes and Devices","volume":"131 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134261831","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Compact process model of temperature dependent amorphization induced by ion implantation 离子注入诱导温度相关非晶化的紧凑过程模型
2010 International Conference on Simulation of Semiconductor Processes and Devices Pub Date : 2010-10-14 DOI: 10.1109/SISPAD.2010.5604529
Alexander Schmidt, I. Jang, Tai-kyung Kim, Keun-Ho Lee, Young-Kwan Park, Moon-Hyun Yoo, C. Chung
{"title":"Compact process model of temperature dependent amorphization induced by ion implantation","authors":"Alexander Schmidt, I. Jang, Tai-kyung Kim, Keun-Ho Lee, Young-Kwan Park, Moon-Hyun Yoo, C. Chung","doi":"10.1109/SISPAD.2010.5604529","DOIUrl":"https://doi.org/10.1109/SISPAD.2010.5604529","url":null,"abstract":"A compact process model of the thickness of amorphous layer generated by high dose ion implantation was developed. The model takes into account implantation temperature that has strong effect on the damage accumulation and amorphization dynamics. The model is based on the results of Kinetic Monte Carlo simulation of implantation process and provides means for fast and precise calculation of amorphous layer thickness created by most common species used in semiconductor technology, with a wide range of implantation energies, doses and temperatures.","PeriodicalId":331098,"journal":{"name":"2010 International Conference on Simulation of Semiconductor Processes and Devices","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134345509","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Quantum transport of Dirac fermions in graphene field effect transistors 石墨烯场效应晶体管中狄拉克费米子的量子输运
2010 International Conference on Simulation of Semiconductor Processes and Devices Pub Date : 2010-10-14 DOI: 10.1109/SISPAD.2010.5604585
V. Hung Nguyen, A. Bournel, C. Chassat, P. Dollfus
{"title":"Quantum transport of Dirac fermions in graphene field effect transistors","authors":"V. Hung Nguyen, A. Bournel, C. Chassat, P. Dollfus","doi":"10.1109/SISPAD.2010.5604585","DOIUrl":"https://doi.org/10.1109/SISPAD.2010.5604585","url":null,"abstract":"We present a quantum transport simulation of graphene field-effect transistors based on the self consistent solution of 2D-Poisson solver and Dirac equation within the non-equilibrium Green's function formalism. The device operation of double gate 2D-graphene field effect transistors is investigated. The study emphasizes the band-to-band and Klein tunneling processes of massless carriers and the resulting features of the electrostatic modulation of I-V characteristics. A transconductance as high as a few hundreds of μS/μm is observed, despite low on/off current ratios. The model is also extended to massive carriers, which allows us to show the on/off current ratio enhancement due to finite bandgap. The obtained results suggest the feasibility of 2D-graphene devices for analogue applications.","PeriodicalId":331098,"journal":{"name":"2010 International Conference on Simulation of Semiconductor Processes and Devices","volume":"122 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129115346","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 18
Coupled Monte Carlo simulation of transient electron-phonon transport in nanoscale devices 纳米器件中瞬态电子-声子输运的耦合蒙特卡罗模拟
2010 International Conference on Simulation of Semiconductor Processes and Devices Pub Date : 2010-10-14 DOI: 10.1109/SISPAD.2010.5604561
Y. Kamakura, N. Mori, K. Taniguchi, T. Zushi, Takanobu Watanabe
{"title":"Coupled Monte Carlo simulation of transient electron-phonon transport in nanoscale devices","authors":"Y. Kamakura, N. Mori, K. Taniguchi, T. Zushi, Takanobu Watanabe","doi":"10.1109/SISPAD.2010.5604561","DOIUrl":"https://doi.org/10.1109/SISPAD.2010.5604561","url":null,"abstract":"Using a coupled Monte Carlo method for solving both electron and phonon Boltzmann transport equations, the transient electrothermal behaviors of nanoscale Si n-i-n device are simulated. The nonequilibrium optical phonon distribution is characterized by a temperature different from that of the acoustic phonons, and these two temperatures show different characteristics not only in the steady state, but also in transient conditions. It has been also suggested that the simulated transient response of the phonon temperatures can be practically described by the equivalent thermal circuit model, which is useful for, e.g., projecting the NBTI lifetime during the realistic circuit operations.","PeriodicalId":331098,"journal":{"name":"2010 International Conference on Simulation of Semiconductor Processes and Devices","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130436454","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
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