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Proceedings., International Test Conference最新文献

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Fixed-biased pseudorandom built-in self-test for random pattern resistant circuits 固定偏置伪随机内置自检抗随机模式电路
Proceedings., International Test Conference Pub Date : 1994-10-02 DOI: 10.1109/TEST.1994.528042
M. F. AlShaibi, C. Kime
{"title":"Fixed-biased pseudorandom built-in self-test for random pattern resistant circuits","authors":"M. F. AlShaibi, C. Kime","doi":"10.1109/TEST.1994.528042","DOIUrl":"https://doi.org/10.1109/TEST.1994.528042","url":null,"abstract":"In this paper we present a new test per clock BIST technique that provides 100% fault coverage of detectable single stuck-at faults for random pattern resistant circuits with low test application time and limited hardware overhead. The technique uses selective bit-fixing plus biased pseudorandom patterns and is referred to as fixed-biased pseudorandom BIST. An automatic design tool (FBIST) specifies the necessary information for implementation of the BIST hardware. The amount of hardware overhead introduced is controlled by user specified parameters and can therefore meet varying design specifications. Since the proposed technique relies on bit-fixing, we present a new scan cell which supports bit-fixing. Results are presented for combinational benchmark circuits and comparisons made with prior techniques with respect to test application time and hardware overhead.","PeriodicalId":309921,"journal":{"name":"Proceedings., International Test Conference","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121227204","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 39
Low power mode and IEEE 1149.1 compliance: a low power solution 低功耗模式和IEEE 1149.1合规性:低功耗解决方案
Proceedings., International Test Conference Pub Date : 1994-10-02 DOI: 10.1109/TEST.1994.528011
A. Crouch, R. Ramus, C. Maunder
{"title":"Low power mode and IEEE 1149.1 compliance: a low power solution","authors":"A. Crouch, R. Ramus, C. Maunder","doi":"10.1109/TEST.1994.528011","DOIUrl":"https://doi.org/10.1109/TEST.1994.528011","url":null,"abstract":"The requirements of a low power mode, built into complex VLSI IC's such as microprocessors, seem to conflict with the IEEE 1149.1 Standard (JTAG). The perception that the TAP Pins-T~R~S~T~, TMS, and TDI-must be equipped with power-consuming pullup resistors or that low power and 1149.1 modes of operation are mutually exclusive is erroneous. Certain techniques can be used during the design and implementation of the TAP and the TAP controller that will allow the IC to enter low power mode without interference or unnecessary power consumption from the JTAG logic and will allow JTAG operations during low power mode while maintaining full compliance to the 1149.1 standard.","PeriodicalId":309921,"journal":{"name":"Proceedings., International Test Conference","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116425662","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Detection and correction of systematic type I test errors through concurrent engineering 采用并行工程方法对系统I类测试误差进行检测与修正
Proceedings., International Test Conference Pub Date : 1994-10-02 DOI: 10.1109/TEST.1994.527996
William R. Kosar
{"title":"Detection and correction of systematic type I test errors through concurrent engineering","authors":"William R. Kosar","doi":"10.1109/TEST.1994.527996","DOIUrl":"https://doi.org/10.1109/TEST.1994.527996","url":null,"abstract":"Systematic Type I test errors in the integrated circuit production test environment are analyzed with an emphasis on wafer level test problems. Effective use of concurrent engineering procedures is shown to be a critical factor in the rapid detection and solution of these problems.","PeriodicalId":309921,"journal":{"name":"Proceedings., International Test Conference","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126853579","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Test strategies for a family of complex MCMs 一系列复杂mcm的测试策略
Proceedings., International Test Conference Pub Date : 1994-10-02 DOI: 10.1109/TEST.1994.527985
A. Flint
{"title":"Test strategies for a family of complex MCMs","authors":"A. Flint","doi":"10.1109/TEST.1994.527985","DOIUrl":"https://doi.org/10.1109/TEST.1994.527985","url":null,"abstract":"The development of MCM test practices from chip and board test practices is summarized. The general philosophy behind MCM test strategy selection is given. A family of complex MCMs providing computer system building blocks is described. The design features related to testability and test coverage are detailed. Then, test strategies developed for each MCM are related, with emphasis on the improvements in fault coverage and diagnostic resolution provided by attention to design-for-testability.","PeriodicalId":309921,"journal":{"name":"Proceedings., International Test Conference","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126464028","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
Practical test methods for verification of the EDRAM 验证EDRAM的实用测试方法
Proceedings., International Test Conference Pub Date : 1994-10-02 DOI: 10.1109/TEST.1994.527972
Kent Stalnaker
{"title":"Practical test methods for verification of the EDRAM","authors":"Kent Stalnaker","doi":"10.1109/TEST.1994.527972","DOIUrl":"https://doi.org/10.1109/TEST.1994.527972","url":null,"abstract":"The Ramtron EDRAM is a 4 Mb dynamic RAM with 2 Kb static RAM cache. It is designed for 35 ns random access times, 15 ns cache cycle times with 5 ns pulse widths and includes logic functions not found on standard DRAM's. The simple solution to testing the part is a 67 to 100 MHz machine, but a more creative solution requires the use of only slightly more creative techniques. The EDRAM, while having its own unique requirements for guaranteeing proper operation, is a part that can be fully tested an standard memory test equipment capable of 30 to 5 MHz operation with an algorithmic pattern generator.","PeriodicalId":309921,"journal":{"name":"Proceedings., International Test Conference","volume":"2015 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127735842","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Automated logic synthesis of random pattern testable circuits 随机模式测试电路的自动逻辑合成
Proceedings., International Test Conference Pub Date : 1994-10-02 DOI: 10.1109/TEST.1994.527948
N. Touba, E. McCluskey
{"title":"Automated logic synthesis of random pattern testable circuits","authors":"N. Touba, E. McCluskey","doi":"10.1109/TEST.1994.527948","DOIUrl":"https://doi.org/10.1109/TEST.1994.527948","url":null,"abstract":"Previous approaches to designing random pattern testable circuits use post-synthesis test point insertion to eliminate random pattern resistant (r.p.r.) faults. The approach taken in this paper is to consider random pattern testability during logic synthesis. An automated logic synthesis procedure is presented which takes as an input a two-level representation of a circuit and a constraint on the minimum fault detection probability (threshold below which faults are considered r.p.r.) and generates a multilevel implementation that satisfies the constraint while minimizing the literal count. The procedure identifies r.p.r. faults and attempts to \"eliminate\" them through algebraic factoring. If that is not possible, then test points are inserted during the synthesis process in a way that minimizes the number of test points that are required. Results are shown for benchmark circuits which indicate that the proposed procedure can generally reduce the random pattern test length by at least an order of magnitude with only a small area overhead.","PeriodicalId":309921,"journal":{"name":"Proceedings., International Test Conference","volume":"68 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127578765","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 34
A test system architecture to reduce transmission line effects during high speed testing 一种在高速测试过程中减少传输线影响的测试系统架构
Proceedings., International Test Conference Pub Date : 1994-10-02 DOI: 10.1109/TEST.1994.528016
Marc Mydill
{"title":"A test system architecture to reduce transmission line effects during high speed testing","authors":"Marc Mydill","doi":"10.1109/TEST.1994.528016","DOIUrl":"https://doi.org/10.1109/TEST.1994.528016","url":null,"abstract":"Testing high speed CMOS devices in a \"non-terminated\" transmission line environment can result in significant timing errors due to signal reflections. These errors can be substantially reduced with a test system designed to minimize the distance between device outputs and tester comparator inputs.","PeriodicalId":309921,"journal":{"name":"Proceedings., International Test Conference","volume":"25 10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127444611","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
Automatic failure analysis system for high density DRAM 高密度DRAM自动故障分析系统
Proceedings., International Test Conference Pub Date : 1994-10-02 DOI: 10.1109/TEST.1994.527995
Sangchul Oh, Jae-Ho Kim, Ho-Jeong Choi, S. Choi, K. Park, Jong-Woo Park, Wha-Joon Lee
{"title":"Automatic failure analysis system for high density DRAM","authors":"Sangchul Oh, Jae-Ho Kim, Ho-Jeong Choi, S. Choi, K. Park, Jong-Woo Park, Wha-Joon Lee","doi":"10.1109/TEST.1994.527995","DOIUrl":"https://doi.org/10.1109/TEST.1994.527995","url":null,"abstract":"In this paper, the automatic failure analysis method based on the random bit failure causing the major yield drop in DRAM and the analysis system named \"SEC FAILURE ANALYSIS SYSTEM\" are discussed. This system is developed for the accurate and rapid electrical analysis of the failure in a statistical manner in order to make a quick feedback to the manufacturing process.","PeriodicalId":309921,"journal":{"name":"Proceedings., International Test Conference","volume":"134 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127359994","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
ASIC test cost/strategy trade-offs ASIC测试成本/策略权衡
Proceedings., International Test Conference Pub Date : 1994-10-02 DOI: 10.1109/TEST.1994.527940
D. L. Wheater, P. Nigh, J. Mechler, Luke Lacroix
{"title":"ASIC test cost/strategy trade-offs","authors":"D. L. Wheater, P. Nigh, J. Mechler, Luke Lacroix","doi":"10.1109/TEST.1994.527940","DOIUrl":"https://doi.org/10.1109/TEST.1994.527940","url":null,"abstract":"Supplying cost effective testing for large application specific integrated circuits (ASICs) is one of the key challenges facing the semiconductor industry. Projections suggest that it will not be cost effective to continue in the current test direction. ASIC suppliers must be able to offer a flexible, cost-effective set of test solutions that will meet a variety of customer requirements. This paper presents some of the trade-offs used in developing optimal test strategies.","PeriodicalId":309921,"journal":{"name":"Proceedings., International Test Conference","volume":"109 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122698868","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Development of a class 1 QTAG monitor 1类QTAG监视器的开发
Proceedings., International Test Conference Pub Date : 1994-10-02 DOI: 10.1109/TEST.1994.527952
K. Baker, A. Bratt, A. Richardson, A. Welbers
{"title":"Development of a class 1 QTAG monitor","authors":"K. Baker, A. Bratt, A. Richardson, A. Welbers","doi":"10.1109/TEST.1994.527952","DOIUrl":"https://doi.org/10.1109/TEST.1994.527952","url":null,"abstract":"This paper describes the development by the authors of an I/sub DDQ/ monitor for test fixtures based on the provisional QTAG (Quality Test Action Group) standard. The monitor design project is a proof of concept study for the most demanding class 1 type current monitors defined by QTAG. In the paper the historical background to Philips' support for QTAG is outlined and why the company believes that monitors on test fixtures are currently more practical for many applications than either on-chip I/sub DDQ/ monitors or ATE based measurement systems.","PeriodicalId":309921,"journal":{"name":"Proceedings., International Test Conference","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127670418","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 20
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