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Proceedings., International Test Conference最新文献

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Navigating test access in systems 导航系统中的测试访问
Proceedings., International Test Conference Pub Date : 1994-10-02 DOI: 10.1109/TEST.1994.528052
L. Whetsel
{"title":"Navigating test access in systems","authors":"L. Whetsel","doi":"10.1109/TEST.1994.528052","DOIUrl":"https://doi.org/10.1109/TEST.1994.528052","url":null,"abstract":"Hierarchical navigation modes should allow for: (1) a simple busing structure capable of dynamically routing an 1149.1 test bus within any system hierarchy, (2) a protocol, transparent to 1149.1, capable of directing the routing process and confirming the connection made, (3) a method of transmitting 1149.1 test patterns through a routed connection without having to reformat or translate the patterns, and (4) a method of executing data transfer operations through a routed connection transparent to 1149. 1. It is important to note that only one of the three test access methods can provide these hierarchical navigation features, Hierarchical ASP (HASP)C41.","PeriodicalId":309921,"journal":{"name":"Proceedings., International Test Conference","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124887727","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
An approach to accelerate scan testing in IEEE 1149.1 architectures 一种加速IEEE 1149.1架构扫描测试的方法
Proceedings., International Test Conference Pub Date : 1994-10-02 DOI: 10.1109/TEST.1994.527965
L. Whetsel
{"title":"An approach to accelerate scan testing in IEEE 1149.1 architectures","authors":"L. Whetsel","doi":"10.1109/TEST.1994.527965","DOIUrl":"https://doi.org/10.1109/TEST.1994.527965","url":null,"abstract":"This paper describes an approach which can accelerate scan testing of combinational and sequential circuits within IEEE 1149.1 architectures. The approach can be used at both IC and system test levels, however most of the test time reduction benefits of this approach are seen at the system level.","PeriodicalId":309921,"journal":{"name":"Proceedings., International Test Conference","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125024695","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Fastpath: a path-delay test generator for standard scan designs 快速路径:用于标准扫描设计的路径延迟测试发生器
Proceedings., International Test Conference Pub Date : 1994-10-02 DOI: 10.1109/TEST.1994.527946
Bill Underwood, Wai-on Law, Sungho Kang, H. Konuk
{"title":"Fastpath: a path-delay test generator for standard scan designs","authors":"Bill Underwood, Wai-on Law, Sungho Kang, H. Konuk","doi":"10.1109/TEST.1994.527946","DOIUrl":"https://doi.org/10.1109/TEST.1994.527946","url":null,"abstract":"Fastpath generates non-robust, robust or single-path-sensitization hazard-free robust path-delay tests for standard scan designs including high-impedance elements and functionally-described blocks. Results show effective and memory-efficient operation.","PeriodicalId":309921,"journal":{"name":"Proceedings., International Test Conference","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121996482","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 70
Goal-directed vector generation using sample ICs 目标导向矢量生成使用样本ic
Proceedings., International Test Conference Pub Date : 1994-10-02 DOI: 10.1109/TEST.1994.528027
D. Raymond, Philip J. Stringer, H. W. Ng, M. Mitsumata, Robert Burk
{"title":"Goal-directed vector generation using sample ICs","authors":"D. Raymond, Philip J. Stringer, H. W. Ng, M. Mitsumata, Robert Burk","doi":"10.1109/TEST.1994.528027","DOIUrl":"https://doi.org/10.1109/TEST.1994.528027","url":null,"abstract":"This paper describes a test-generation method that automatically creates efficient, high-quality vector sequences that catch ASIC pin faults at in-circuit board test. The method works with a sample IC. Simulation models are not required.","PeriodicalId":309921,"journal":{"name":"Proceedings., International Test Conference","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115512483","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
An intelligent software-integrated environment of IC test 一种智能集成电路测试软件集成环境
Proceedings., International Test Conference Pub Date : 1994-10-02 DOI: 10.1109/TEST.1994.528004
Yuning Sun, Xiaoming Wang, W. Shi
{"title":"An intelligent software-integrated environment of IC test","authors":"Yuning Sun, Xiaoming Wang, W. Shi","doi":"10.1109/TEST.1994.528004","DOIUrl":"https://doi.org/10.1109/TEST.1994.528004","url":null,"abstract":"The migration and simulation of IC test programs among the heterogeneous ATE systems are a very difficult task. An unifying IC test software-integrated environment from simulation to test for digital circuit has been developed. The environment, TeDS which is designed by using object-oriented paradigm, supports two kinds of CAD systems and three kinds of ATE (Automatic Test Equipment). The paper focuses on issues and techniques in developing TeDS based on object-oriented paradigm.","PeriodicalId":309921,"journal":{"name":"Proceedings., International Test Conference","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116629837","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
The effect on quality of non-uniform fault coverage and fault probability 对非均匀故障覆盖率和故障概率质量的影响
Proceedings., International Test Conference Pub Date : 1994-10-02 DOI: 10.1109/TEST.1994.528020
P. Maxwell, R. Aitken, L. Huisman
{"title":"The effect on quality of non-uniform fault coverage and fault probability","authors":"P. Maxwell, R. Aitken, L. Huisman","doi":"10.1109/TEST.1994.528020","DOIUrl":"https://doi.org/10.1109/TEST.1994.528020","url":null,"abstract":"This paper addresses problems associated with the production and interpretation of traditional fault coverage numbers. The first part addresses the issue of non-uniform distribution of detected faults. It is shown that there is a large difference in final quality between covering the chip all over and leaving parts relatively untested, even if the coverage is the same in both cases. The second part deals with the use of weighted, rather than unweighted fault coverages and investigates the use of readily-available extracted capacitance information to produce a weighted fault coverage which is more useful for producing quality estimates, without having to perform a full defect analysis. Results show significant differences in weighted versus unweighted coverages, and also that these differences can be in either direction.","PeriodicalId":309921,"journal":{"name":"Proceedings., International Test Conference","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121625312","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 24
An automatic test pattern generator for large sequential circuits based on Genetic Algorithms 基于遗传算法的大型顺序电路测试图自动生成
Proceedings., International Test Conference Pub Date : 1994-10-02 DOI: 10.1109/TEST.1994.527955
P. Prinetto, M. Rebaudengo, M. Reorda
{"title":"An automatic test pattern generator for large sequential circuits based on Genetic Algorithms","authors":"P. Prinetto, M. Rebaudengo, M. Reorda","doi":"10.1109/TEST.1994.527955","DOIUrl":"https://doi.org/10.1109/TEST.1994.527955","url":null,"abstract":"This paper is concerned with the question of automated test pattern generation for large synchronous sequential circuits and describes an approach based on Genetic Algorithms suitable for even the largest benchmark circuits, together with a prototype system named GATTO. Its effectiveness (in terms of result quality and CPU time requirements) for circuits previously unmanageable is illustrated. The flexibility of the new approach enables users to easily trade off fault coverage and CPU time to suit their needs.","PeriodicalId":309921,"journal":{"name":"Proceedings., International Test Conference","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115105390","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 89
Feasibility study of smart substrate multichip modules 智能基板多芯片模块的可行性研究
Proceedings., International Test Conference Pub Date : 1994-10-02 DOI: 10.1109/TEST.1994.527934
A. Gattiker, Wojciech Maly
{"title":"Feasibility study of smart substrate multichip modules","authors":"A. Gattiker, Wojciech Maly","doi":"10.1109/TEST.1994.527934","DOIUrl":"https://doi.org/10.1109/TEST.1994.527934","url":null,"abstract":"This paper analyzes the feasibility of MCMs using active silicon substrates with built-in resting circuitry. It identifies the domain of applicability of such MCMs and points to limitations of the \"Known Good Die\" approach.","PeriodicalId":309921,"journal":{"name":"Proceedings., International Test Conference","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123373466","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
Testability strategy of the Alpha AXP 21164 microprocessor Alpha AXP 21164微处理器的可测试性策略
Proceedings., International Test Conference Pub Date : 1994-10-02 DOI: 10.1109/TEST.1994.527935
D. Bhavsar, J. Edmondson
{"title":"Testability strategy of the Alpha AXP 21164 microprocessor","authors":"D. Bhavsar, J. Edmondson","doi":"10.1109/TEST.1994.527935","DOIUrl":"https://doi.org/10.1109/TEST.1994.527935","url":null,"abstract":"This paper describes the testability strategy and design-for-test features of the Alpha AXP 21164 microprocessor. It discusses the specific testability and manufacturability issues of the chip and the innovative solutions employed to solve them.","PeriodicalId":309921,"journal":{"name":"Proceedings., International Test Conference","volume":"337 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115890242","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 31
Test station workcell controller and resource relationship design 试验站工作单元控制器与资源关系设计
Proceedings., International Test Conference Pub Date : 1994-10-02 DOI: 10.1109/TEST.1994.528025
S. Erjavic
{"title":"Test station workcell controller and resource relationship design","authors":"S. Erjavic","doi":"10.1109/TEST.1994.528025","DOIUrl":"https://doi.org/10.1109/TEST.1994.528025","url":null,"abstract":"Taking advantage of distributed computing tools and recognizing the integrated importance of people and equipment in manufacturing allows for the development of a highly capable and complex test station workcell control environment. The workcell architecture is focused on the collection of process resource data for analysis against and improvement upon existing performance models.","PeriodicalId":309921,"journal":{"name":"Proceedings., International Test Conference","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123847671","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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