一种加速IEEE 1149.1架构扫描测试的方法

Proceedings., International Test Conference Pub Date : 1994-10-02 DOI:10.1109/TEST.1994.527965

L. Whetsel

{"title":"一种加速IEEE 1149.1架构扫描测试的方法","authors":"L. Whetsel","doi":"10.1109/TEST.1994.527965","DOIUrl":null,"url":null,"abstract":"This paper describes an approach which can accelerate scan testing of combinational and sequential circuits within IEEE 1149.1 architectures. The approach can be used at both IC and system test levels, however most of the test time reduction benefits of this approach are seen at the system level.","PeriodicalId":309921,"journal":{"name":"Proceedings., International Test Conference","volume":"7 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1994-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"An approach to accelerate scan testing in IEEE 1149.1 architectures\",\"authors\":\"L. Whetsel\",\"doi\":\"10.1109/TEST.1994.527965\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper describes an approach which can accelerate scan testing of combinational and sequential circuits within IEEE 1149.1 architectures. The approach can be used at both IC and system test levels, however most of the test time reduction benefits of this approach are seen at the system level.\",\"PeriodicalId\":309921,\"journal\":{\"name\":\"Proceedings., International Test Conference\",\"volume\":\"7 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1994-10-02\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings., International Test Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/TEST.1994.527965\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings., International Test Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/TEST.1994.527965","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 2

摘要

本文介绍了一种在IEEE 1149.1体系结构下加速组合电路和顺序电路扫描测试的方法。这种方法既可以用于IC测试，也可以用于系统测试，但是这种方法减少测试时间的好处主要体现在系统级别。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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An approach to accelerate scan testing in IEEE 1149.1 architectures

This paper describes an approach which can accelerate scan testing of combinational and sequential circuits within IEEE 1149.1 architectures. The approach can be used at both IC and system test levels, however most of the test time reduction benefits of this approach are seen at the system level.

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Proceedings., International Test Conference

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