{"title":"On path delay testing in a standard scan environment","authors":"P. Varma","doi":"10.1109/TEST.1994.527947","DOIUrl":"https://doi.org/10.1109/TEST.1994.527947","url":null,"abstract":"This paper discusses delay fault test generation methodologies that avoid the area and performance overhead of enhanced scan elements by the use of scan and functional justification techniques. Issues with the use of scan justification and functional justification in a standard edge-triggered single clock scan environment are discussed. A functional justification based path delay test generator for circuits designed using standard scan elements is described. This test generator uses a calculus that allows circuits containing internal tri-state elements and bi-directional ports to be supported. Clock suppression techniques are employed to minimize state justification requirements.","PeriodicalId":309921,"journal":{"name":"Proceedings., International Test Conference","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115399665","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Brian Chess, Anthony Freitas, F. Ferguson, T. Larrabee
{"title":"Testing CMOS logic gates for: realistic shorts","authors":"Brian Chess, Anthony Freitas, F. Ferguson, T. Larrabee","doi":"10.1109/TEST.1994.527981","DOIUrl":"https://doi.org/10.1109/TEST.1994.527981","url":null,"abstract":"It is assumed that tests generated using the single stuck-at fault model will implicitly detect the vast majority of fault-causing defects within logic elements. This may not be the case. In this paper we characterize the possible shorts in the combinational cells in a standard cell library. The characterization includes errors on the cell outputs, errors on the cell inputs, and excessive quiescent current. The characterization provides input vectors to stimulate these errors. After characterizing the faults that occur due to possible electrical shorts, we compare the coverage of the logic faults using a single stuck-at test set and tests developed specifically to detect these shorts. We discuss the effectiveness of I/sub DDQ/ testing for these faults.","PeriodicalId":309921,"journal":{"name":"Proceedings., International Test Conference","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125031164","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
T. Burch, J. Hartmann, G. Hotz, M. Krallmann, U. Nikolaus, S. Reddy, U. Sparmann
{"title":"A hierarchical environment for interactive test engineering","authors":"T. Burch, J. Hartmann, G. Hotz, M. Krallmann, U. Nikolaus, S. Reddy, U. Sparmann","doi":"10.1109/TEST.1994.527988","DOIUrl":"https://doi.org/10.1109/TEST.1994.527988","url":null,"abstract":"Conventional tools for test generation and fault simulation appear to the test engineer as black boxes which neither communicate their results in a convenient way, nor allow for any interactive guidance by the test engineer. In contrast, the HIT system presented in this paper supports interactive test engineering, thus combining the power of state level test generation algorithms with the high level knowledge of the test engineer. Since the HIT system has been integrated into a hierarchical design system (CADIC), the results of test tools can be visualized at the hierarchical circuit specifications given by the designer. Based on this visualization, the critical, untestable areas of the circuit can be easily located. Additionally, the test engineer is supplied with flexible test tools, which allow to actively guide the test development process. Thus, module specific test strategies can be applied or high level knowledge about the functionality of the overall circuit can be 'communicated' to speed-up test generation and redundancy identification. An application example shows that with simple strategies for interactive test engineering the results of test generation can be improved dramatically.","PeriodicalId":309921,"journal":{"name":"Proceedings., International Test Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125852015","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Improving software testability with assertion insertion","authors":"Hwei Yin, J. Bieman","doi":"10.1109/TEST.1994.528030","DOIUrl":"https://doi.org/10.1109/TEST.1994.528030","url":null,"abstract":"Executable assertions can be inserted into a program to find software faults. Unfortunately, the process of designing and embedding these assertions can be expensive and time consuming. We have developed the C-Patrol tool to reduce the overhead of using assertions in C programs. C-Patrol allows a developer to reference a set of previously defined assertions, written in virtual C, bind assertion parameters, and direct the placement of the assertions by a pre-processor.","PeriodicalId":309921,"journal":{"name":"Proceedings., International Test Conference","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123783682","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Transforming behavioral specifications to facilitate synthesis of testable designs","authors":"S. Dey, M. Potkonjak","doi":"10.1109/TEST.1994.527949","DOIUrl":"https://doi.org/10.1109/TEST.1994.527949","url":null,"abstract":"Recently, several high level synthesis approaches have been proposed to synthesize testable data paths from behavioral specifications. This paper introduces a novel technique to transform behavioral specifications, such that an existing behavioral test synthesis system can generate area-efficient, testable designs with significantly lower partial scan overhead. Experimental results demonstrate the significant savings in partial scan overhead when the transformation is applied before using the behavioral test synthesis system to synthesize 100% test-efficient designs.","PeriodicalId":309921,"journal":{"name":"Proceedings., International Test Conference","volume":"72 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122020039","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Defect classes-an overdue paradigm for CMOS IC testing","authors":"C. Hawkins, J. Soden, A. Righter, F. Ferguson","doi":"10.1109/TEST.1994.527983","DOIUrl":"https://doi.org/10.1109/TEST.1994.527983","url":null,"abstract":"The IC test industry has struggled for move than 30 years to establish a test approach that would guarantee a low defect level to the customer. We propose a comprehensive strategy for testing CMOS ICs that uses defect classes based on measured defect electrical properties. Defect classes differ from traditional fault models. Our defect class approach requires that the rest strategy match the defect electrical properties, while fault models require that IC defects match the fault definition. We use data from Sandia Labs failure analysis and test facilities and from public literature. We describe test pattern requirements for each defect class and propose a test paradigm.","PeriodicalId":309921,"journal":{"name":"Proceedings., International Test Conference","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122168013","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Testing 256k word/spl times/16 bit Cache DRAM (CDRAM)","authors":"Y. Konishi, T. Ogawa, M. Kumanoya","doi":"10.1109/TEST.1994.527970","DOIUrl":"https://doi.org/10.1109/TEST.1994.527970","url":null,"abstract":"Cache DRAM (CDRAM) is a promising high speed memory which can eliminate \"memory bottleneck\" in a computer system and can realize \"unified memory\" for a multi-media system. Test of a CDRAM is broken down to several sub-test steps. Testing a CDRAM comprises separated test and concurrent test of SRAM and DRAM. Dual PGs of ATE are powerful tools both for high speed and concurrent operation tests.","PeriodicalId":309921,"journal":{"name":"Proceedings., International Test Conference","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130367283","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
F. Bouwman, T. Zwemstra, Sonny Hartanto, K. Baker, Jan Koopmans
{"title":"Application of joint time-frequency analysis in mixed signal testing","authors":"F. Bouwman, T. Zwemstra, Sonny Hartanto, K. Baker, Jan Koopmans","doi":"10.1109/TEST.1994.528021","DOIUrl":"https://doi.org/10.1109/TEST.1994.528021","url":null,"abstract":"Combining the processing power and flexibility of modern DSP based test-systems with the broad area of joint time-frequency signal analysis yields a potentially promising new line of research in the area of analog and mixed-signal test. This paper discusses some practical examples of applying analyses tools, like the short-time-Fourier and wavelet transform for testing ADCs. The research focuses on gaining insight into the advantages of these analysis techniques, for instance in revealing device performance deviations or faults which are not detectable using conventional analysis tools, and also the ability to cover the same faults in a single test which would have taken several tests using conventional methods.","PeriodicalId":309921,"journal":{"name":"Proceedings., International Test Conference","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126304578","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Modeling for structured system interconnect test","authors":"Frank W. Angelotti","doi":"10.1109/TEST.1994.527944","DOIUrl":"https://doi.org/10.1109/TEST.1994.527944","url":null,"abstract":"With the acceptance of test standards such as IEEE 1149.1, the potential for structured methods for system test is growing rapidly. In particular, interconnect testing based on standardized boundary scan structures will be an important component of a future structured system test methodology. A strategy based on building an interconnect topology model of the system under test and using that model to generate interconnect test patterns at test time provides for a level of system test coverage that is difficult or impossible to obtain from methods based on static stored test patterns. This paper discusses the problem of dynamically generating a model of system interconnect topology for use in structured interconnect test generation and analysis. A solution for the most general case is given and some simple system design for test rules that greatly simplify the process are proposed. Several additional solutions which explore some potential trade-offs are discussed. A practical algorithm that requires minimal storage and reasonable computation is proposed.","PeriodicalId":309921,"journal":{"name":"Proceedings., International Test Conference","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127930266","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"An effective BIST scheme for ring-address type FIFOs","authors":"Y. Zorian, A. V. Goor, I. Schanstra","doi":"10.1109/TEST.1994.527979","DOIUrl":"https://doi.org/10.1109/TEST.1994.527979","url":null,"abstract":"FIFO memories impose special test problems because of their built-in addressing restrictions and access limitations. With the increasing usage of FIFOs today, generic algorithms are needed to test stand-alone FIFO chips and embedded FIFO macros. This paper addresses the problem of testing a very popular type of FIFO, namely the ring-address FIFO. It introduces two novel algorithms to test this type of FIFO. Both algorithms provide full fault coverage for a comprehensive fault model. The first algorithm uses a generic test approach in the sense that it does not require any change to the FIFO hardware. Whereas, the second algorithm is DFT-based. It assumes access to a FIFO design and suggests minor DFT modifications, in order to reduce the test complexity from O(n/sup 2/) to O(n). The BIST architecture of the DFT-based algorithm, which has recently been utilized in different products, is also described.","PeriodicalId":309921,"journal":{"name":"Proceedings., International Test Conference","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130184941","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
求助内容：
应助结果提醒方式：
京公网安备 11010802042870号
