On path delay testing in a standard scan environment

Abstract

This paper discusses delay fault test generation methodologies that avoid the area and performance overhead of enhanced scan elements by the use of scan and functional justification techniques. Issues with the use of scan justification and functional justification in a standard edge-triggered single clock scan environment are discussed. A functional justification based path delay test generator for circuits designed using standard scan elements is described. This test generator uses a calculus that allows circuits containing internal tri-state elements and bi-directional ports to be supported. Clock suppression techniques are employed to minimize state justification requirements.