{"title":"A test clock reduction method for scan-designed circuits","authors":"Jau-Shien Chang, Chen-Shang Lin","doi":"10.1109/TEST.1994.527967","DOIUrl":"https://doi.org/10.1109/TEST.1994.527967","url":null,"abstract":"In this paper, a novel test clock reduction method is proposed to generate a compact test scheme for scan-designed sequential circuits. The method comprises of two phases. First, from a given compact combinational test set, sequential fault propagation is performed after each scan-in operation to propagate the activated faults and simultaneously detect other undetected faults as many as possible. In the second phase, two active overlapping techniques are developed to maximize the overlap between successive scan-in patterns in pure scan mode. The experimental results show that the number of test clocks are reduced to half of full-scan. Furthermore, in comparison with the mix-mode test generator, TARF (1992) requires 54% more test clocks than ours.","PeriodicalId":309921,"journal":{"name":"Proceedings., International Test Conference","volume":"368 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127584509","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"MCM test trade-offs","authors":"J. Eastman","doi":"10.1109/TEST.1994.527977","DOIUrl":"https://doi.org/10.1109/TEST.1994.527977","url":null,"abstract":"The cost of design-for-test is a key factor when determining whether or not to use MCM technology. Higher-end MCMs must be designed-for-test (DFT) since not implementing DFT is more expensive in the long run. This may not be the case for lower-cost, lower performance MCMs. Among other advantages, MCM technology can offer smaller size, better performance, and lower weight. But the cost of poor DFT implementation can outweigh these advantages. For example, when remapping a PCB design into an MCM using off-the-shelf components without DFT built-in, implementing DFT into the MCM package may require the expensive redesign of chips or the addition of test chips. Then an MCM is designed with ASICs targeted for MCM packaging to begin with, implementing DFT can be relatively inexpensive if the proper DFT tools are available. These factors help determine the trade-off between the amount and cost of DFT against the advantages of using MCM technology. Structural test is the best solution for higher-end modules for bring-up, diagnostic and re-work reasons. For MCMs where a defective assembly still has high value and must be reworked, MCMs must be diagnosed.","PeriodicalId":309921,"journal":{"name":"Proceedings., International Test Conference","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130755502","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Transparent memory testing for pattern sensitive faults","authors":"M. Karpovsky, V. Yarmolik","doi":"10.1109/TEST.1994.528033","DOIUrl":"https://doi.org/10.1109/TEST.1994.528033","url":null,"abstract":"This paper presents a new methodology for RAM testing based on PS(n, k) fault model (the k out of n pattern sensitive fault model). According to the model the contents of any memory cell which belongs to an n-bit memory block, or ability to change the contents, is influenced by the contents of any k-1 cells from this block. This paper includes the investigation of memory testing approaches based on the transparent pseudoexhaustive testing and its approximations by pseudorandom circular tests, which can be used for periodic and manufacturing testing and require lower hardware and time overheads than the standard approaches.","PeriodicalId":309921,"journal":{"name":"Proceedings., International Test Conference","volume":"317 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130745577","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Modeling the effect of ground bounce on noise margin","authors":"M. S. Haydt, R. Owens, S. Mourad","doi":"10.1109/TEST.1994.527960","DOIUrl":"https://doi.org/10.1109/TEST.1994.527960","url":null,"abstract":"In integrated circuits, ground bounce is the voltage developed across the inductance of the power supply leads as a result of the current surge through switching gates. It causes distortion of circuit output waveforms that can interfere with testing. This paper describes a simple circuit model that can be used to estimate the ground bounce waveform that appears on both switching and nonswitching outputs of CMOS circuits as a result of ground bounce. The model includes the effects of several circuit parameters on the waveform and has been validated by extensive Spice simulation.","PeriodicalId":309921,"journal":{"name":"Proceedings., International Test Conference","volume":"119 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133583051","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"An improved method of ADC jitter measurement","authors":"Y. Langard, Jean-Luc Balat, J. Durand","doi":"10.1109/TEST.1994.528023","DOIUrl":"https://doi.org/10.1109/TEST.1994.528023","url":null,"abstract":"This paper describes an original and highly accurate method for measuring analog to digital converters jitter. Previous works cover the \"locked\" histogram test which is generally used to estimate aperture uncertainty. This new method uses substraction techniques in a dual-channel sampling system. Synthesizers phase noise, voltage noise and ADC nonlinearities are removed to give the sum of both ADC's jitter. Then a third ADC is used to determine one ADC jitter value by 3 consecutive measurements. A significant improvement is demonstrated.","PeriodicalId":309921,"journal":{"name":"Proceedings., International Test Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132093028","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"HALT: bridging the gap between theory and practice","authors":"Cheryl Ascarrunz","doi":"10.1109/TEST.1994.527998","DOIUrl":"https://doi.org/10.1109/TEST.1994.527998","url":null,"abstract":"Tandem Computers routinely uses HALT (highly accelerated life test) and ESS (environmental stress screening) strategies to develop more robust designs and achieve higher product quality. This paper discusses the development of this methodology and its widespread applicability to all companies.","PeriodicalId":309921,"journal":{"name":"Proceedings., International Test Conference","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117250759","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Analogue fault simulation based on layout dependent fault models","authors":"R. Harvey, A. Richardson, E. Bruls, K. Baker","doi":"10.1109/TEST.1994.528009","DOIUrl":"https://doi.org/10.1109/TEST.1994.528009","url":null,"abstract":"A testability analysis procedure for complex analogue circuits is presented based on layout dependent fault models extracted from process defect statistics. The technique has been applied to a mixed-signal phase locked loop circuit and a number of test methodologies have been evaluated including the existing production test. It is concluded that the fault coverage achieved by this test can be improved by the use of a supplementary test based on power supply variations.","PeriodicalId":309921,"journal":{"name":"Proceedings., International Test Conference","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125810509","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
M. Calha, Marcelino B. Santos, F. Gonçalves, I. Teixeira, João Paulo Teixeira
{"title":"Back annotation of physical defects into gate-level, realistic faults in digital ICs","authors":"M. Calha, Marcelino B. Santos, F. Gonçalves, I. Teixeira, João Paulo Teixeira","doi":"10.1109/TEST.1994.528018","DOIUrl":"https://doi.org/10.1109/TEST.1994.528018","url":null,"abstract":"IC complexity moves the design activity upwards, into higher levels of abstraction. Product quality requires the move of test activity downwards, down to IC physical level. High quality test requires the ability to cover physical defects. However, circuit complexity makes test preparation, at transistor level, prohibitive. A methodology for back annotation of physical defects into gate level realistic faults, is proposed in this paper. Bridging faults are selected, as they are the most likely faults in present-day process lines. It is shown that realistic faults, associated with routing patterns, can be used to represent the overall fault set, leading to an accurate evaluation of the defect level, used as the test quality indicator. A method to generate gate-level, realistic fault lists from the IC layout is presented, and is validated by simulation results.","PeriodicalId":309921,"journal":{"name":"Proceedings., International Test Conference","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124613433","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Digitizer error extraction in the nonlinearity test","authors":"Luke S. L. Hsieh, Sandeep P. Kumar","doi":"10.1109/TEST.1994.528022","DOIUrl":"https://doi.org/10.1109/TEST.1994.528022","url":null,"abstract":"Measuring distortion using sources and digitizers that are nonlinear presents a difficult testing problem. A novel test method using digital signal processing (DSP) techniques is presented to address the error of the digitizer. A Taylor series representation is used to model the distorted digitizer and the device under test (DUT). A set of simultaneous equations can be constructed by considering the frequency contents of the digitized signal. These simultaneous equations can be solved to eliminate the error of the digitizer and give the nonlinearity of the DUT by itself. Additive Gaussian noise is assumed when analyzing errors in computation and during data acquisition. Simulation and experimental results support the analysis.","PeriodicalId":309921,"journal":{"name":"Proceedings., International Test Conference","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129517116","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Multichip module testing methodologies: what's in; what's not","authors":"K. Posse","doi":"10.1109/TEST.1994.527976","DOIUrl":"https://doi.org/10.1109/TEST.1994.527976","url":null,"abstract":"The multichip module (MCM) is rapidly finding its way into the design of commercial electronic systems. The MCM offers this market opportunities for increasing performance, lowering size and weight, lowering power requirements, lowering costs, and improving the functionality per unit area. These characteristics are much too attractive to pass up and thus has begun a headlong rush to create designs using this wonderful new invention. Therefore, the most important element in the cost-effective manufacturing of multichip modules is the accurate diagnosis of defects. This must include the location and cause of manufacturing defects (shorts, opens, wrong component, etc.), functional defects, and performance or timing defects. Surprisingly, such test methods exist and are being used today. The only difficulty with these techniques is that the module designers must be willing to sacrifice some freedom in their designs to meet the testability requirements of the diagnostic methods chosen. Admittedly, this can be a difficult hurdle to overcome; but overcome it we must in order to produce truly high-quality, low-cost modules.","PeriodicalId":309921,"journal":{"name":"Proceedings., International Test Conference","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121313560","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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