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Proceedings., International Test Conference最新文献

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Parallel pattern fast fault simulation for three-state circuits and bidirectional I/O 三态电路和双向I/O的并行模式快速故障仿真
Proceedings., International Test Conference Pub Date : 1994-10-02 DOI: 10.1109/TEST.1994.528005
J. V. D. Linden, M. Konijnenburg, A. V. Goor
{"title":"Parallel pattern fast fault simulation for three-state circuits and bidirectional I/O","authors":"J. V. D. Linden, M. Konijnenburg, A. V. Goor","doi":"10.1109/TEST.1994.528005","DOIUrl":"https://doi.org/10.1109/TEST.1994.528005","url":null,"abstract":"Industrial circuit designs commonly contain three-state elements, such as buses and drivers, transmission gates, and bidirectional I/O. A 5-valued fast fault simulation method and a 4-valued parallel pattern version that can handle these circuits are presented. Results demonstrate the effectiveness of the proposed methods in the presence of three-state elements, and show but a small performance degradation compared to 2- or 3-valued fault simulation.","PeriodicalId":309921,"journal":{"name":"Proceedings., International Test Conference","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114223052","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
On achieving complete testability of synchronous sequential circuits with synchronizing sequences 用同步序列实现同步顺序电路的完全可测试性
Proceedings., International Test Conference Pub Date : 1994-10-02 DOI: 10.1109/TEST.1994.528050
I. Pomeranz, S. Reddy
{"title":"On achieving complete testability of synchronous sequential circuits with synchronizing sequences","authors":"I. Pomeranz, S. Reddy","doi":"10.1109/TEST.1994.528050","DOIUrl":"https://doi.org/10.1109/TEST.1994.528050","url":null,"abstract":"A completely testable circuit does not have any undetectable or redundant faults. We consider the problem of making synchronous sequential circuits that have synchronizing sequences completely testable for stuck-at faults. The method proposed is based on the removal of logic corresponding not only to redundant faults, but also to some undetectable yet irredundant faults. Thus, the proposed approach reduces the circuit size in addition to reducing or eliminating the extra hardware that may be otherwise necessary to render the circuit completely testable. A theoretical framework for achieving this goal was established earlier (1993). In this work, we give a detailed procedure based on the concepts of the previous work and give experimental results of its application.","PeriodicalId":309921,"journal":{"name":"Proceedings., International Test Conference","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121161192","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 19
QTAG: a standard for test fixture based I/sub DDQ//I/sub SSQ/ monitors QTAG:基于I/sub DDQ//I/sub SSQ/监视器的测试夹具标准
Proceedings., International Test Conference Pub Date : 1994-10-02 DOI: 10.1109/TEST.1994.527950
K. Baker
{"title":"QTAG: a standard for test fixture based I/sub DDQ//I/sub SSQ/ monitors","authors":"K. Baker","doi":"10.1109/TEST.1994.527950","DOIUrl":"https://doi.org/10.1109/TEST.1994.527950","url":null,"abstract":"This paper describes the goals and history of the Quality Test Action Group (QTAG) since if was formed at the 1993 International Test Conference. QTAG was created to provide the industry with a de-facto standard for I/sub DDQ//I/sub SSQ/ monitors on test fixtures for production testing of CMOS ICs. The group was needed because informal discussions between the semiconductor test departments and the ATE vendors over the past decade had failed to generate the ATE based I/sub DDQ/ test instrumentation needed by the semiconductor industry.","PeriodicalId":309921,"journal":{"name":"Proceedings., International Test Conference","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121381441","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 31
Techniques for characterizing DRAMs with a 500 MHz interface 具有500 MHz接口的dram表征技术
Proceedings., International Test Conference Pub Date : 1994-10-02 DOI: 10.1109/TEST.1994.527994
J. Gasbarro, M. Horowitz
{"title":"Techniques for characterizing DRAMs with a 500 MHz interface","authors":"J. Gasbarro, M. Horowitz","doi":"10.1109/TEST.1994.527994","DOIUrl":"https://doi.org/10.1109/TEST.1994.527994","url":null,"abstract":"The advent of high-bandwidth DRAMs poses a number of new challenges for test and characterization. This paper describes a collection of techniques that were used in the design and characterization of a new DRAM architecture with 500 MHz I/O signals. Methods of fixturing and calibration are presented for achieving system accuracies of better than 100 ps. Laboratory techniques for measuring critical circuit parameters such as path delay, clock jitter, current source strength, and pin capacitances are shown as well. These techniques, along with on-chip test logic, which allows the DRAM core to be tested using conventional low-speed memory test equipment, enable full characterization of high bandwidth memories.","PeriodicalId":309921,"journal":{"name":"Proceedings., International Test Conference","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133509503","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Ensuring system traceability to international standards 确保系统可追溯性符合国际标准
Proceedings., International Test Conference Pub Date : 1994-10-02 DOI: 10.1109/TEST.1994.527989
S. Max
{"title":"Ensuring system traceability to international standards","authors":"S. Max","doi":"10.1109/TEST.1994.527989","DOIUrl":"https://doi.org/10.1109/TEST.1994.527989","url":null,"abstract":"ATE Systems have many instruments with many ranges. Testers can have >12,000 specifications which must be traceable to international standards. The described algorithm reduces calibration down time, and guarantees traceable testing.","PeriodicalId":309921,"journal":{"name":"Proceedings., International Test Conference","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132200414","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Reduced scan shift: a new testing method for sequential circuits 减小扫描位移:一种新的顺序电路测试方法
Proceedings., International Test Conference Pub Date : 1994-10-02 DOI: 10.1109/TEST.1994.528007
Y. Higami, S. Kajihara, K. Kinoshita
{"title":"Reduced scan shift: a new testing method for sequential circuits","authors":"Y. Higami, S. Kajihara, K. Kinoshita","doi":"10.1109/TEST.1994.528007","DOIUrl":"https://doi.org/10.1109/TEST.1994.528007","url":null,"abstract":"This paper presents a new testing method for sequential circuits, called reduced scan shift, which generates short test sequences. In this method, only part of flip-flops close to the scan input line are controlled and another part of flip-flops close to the scan output line are observed by scan shift operations as small as possible. For the purpose of reducing scan shift operations, the following points are considered: (1) how to decide target faults which each test vector should detects, (2) how to arrange flip-flops in the scan chain, (3) how to decide the order of test vectors. Experimental results for ISCAS'89 benchmark circuits are given to show the effectiveness of this method.","PeriodicalId":309921,"journal":{"name":"Proceedings., International Test Conference","volume":"88 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122160519","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 32
Non-volatile programmable devices and in-circuit test 非易失性可编程器件和在线测试
Proceedings., International Test Conference Pub Date : 1994-10-02 DOI: 10.1109/TEST.1994.528029
D. Raymond, Dominic F. Haigh, Ray Bodick, Barbara Ryan, Dale McCombs
{"title":"Non-volatile programmable devices and in-circuit test","authors":"D. Raymond, Dominic F. Haigh, Ray Bodick, Barbara Ryan, Dale McCombs","doi":"10.1109/TEST.1994.528029","DOIUrl":"https://doi.org/10.1109/TEST.1994.528029","url":null,"abstract":"Once various obstacles are overcome, board testers can serve as programming stations for in-circuit-writable devices such as FPGAs, microcontrollers, EEPROMs, and flash memories. Manufacturing cost and cycle time can be considerably reduced.","PeriodicalId":309921,"journal":{"name":"Proceedings., International Test Conference","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130254710","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Membrane probe technology for MCM Known-Good-Die MCM已知好模的膜探针技术
Proceedings., International Test Conference Pub Date : 1994-10-02 DOI: 10.1109/TEST.1994.527932
T. Ueno, Y. Kondoh
{"title":"Membrane probe technology for MCM Known-Good-Die","authors":"T. Ueno, Y. Kondoh","doi":"10.1109/TEST.1994.527932","DOIUrl":"https://doi.org/10.1109/TEST.1994.527932","url":null,"abstract":"A new type of membrane probe, which might be called a Universal Membrane Probe (UMP), as a standard Known-Good-Die (KGD) solution for Multichip Module (MCM) manufacture is described. The membrane consists of TAB tape mounted with an array of several thousands micro-bumps. The bumps are connected in a radial pattern and the pitch of the bumps is equal to the pitch of the I/O pads in LSIs. The advantage of this new membrane is that a single wiring pattern is applicable to many die designs without the need for customizing. In this paper, two KGD applications of the new membrane are investigated, one is a wafer probe and the other a burn-in socket.","PeriodicalId":309921,"journal":{"name":"Proceedings., International Test Conference","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121666061","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Calculating error of measurement on high speed microprocessor test 高速微处理器测试测量误差的计算
Proceedings., International Test Conference Pub Date : 1994-10-02 DOI: 10.1109/TEST.1994.528026
Tamorah Comard, Madhukar Joshi, D. Morin, K. Sprague
{"title":"Calculating error of measurement on high speed microprocessor test","authors":"Tamorah Comard, Madhukar Joshi, D. Morin, K. Sprague","doi":"10.1109/TEST.1994.528026","DOIUrl":"https://doi.org/10.1109/TEST.1994.528026","url":null,"abstract":"Accuracy and precision are desirable properties of any test process. Understanding test process capability can help ensure that high speed microprocessors are binned at their proper speed. This paper discusses a practical example of how a designed experiment was used to determine the test process speed sorting error of measurement of the Alpha AXP, the industry's fastest microprocessor, tested at Digital Equipment Corporation's Hudson, MA manufacturing site. Knowing error of measurement allowed effective guardbands to be established to guarantee specified performance in the context of the supplier's and consumer's risks. A series of test process improvements resulted from the follow-up work suggested by the experiment.","PeriodicalId":309921,"journal":{"name":"Proceedings., International Test Conference","volume":"272 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115969158","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
An analog multi-tone signal generator for built-in-self-test applications 模拟多音信号发生器内置自检应用
Proceedings., International Test Conference Pub Date : 1994-10-02 DOI: 10.1109/TEST.1994.528010
A. Lu, G. Roberts
{"title":"An analog multi-tone signal generator for built-in-self-test applications","authors":"A. Lu, G. Roberts","doi":"10.1109/TEST.1994.528010","DOIUrl":"https://doi.org/10.1109/TEST.1994.528010","url":null,"abstract":"This paper presents the design of an analog oscillator capable of generating multi-tone signals by encoding the information in an oversampled delta-sigma modulated bit-stream. With the exception of an imprecise lowpass filter, the proposed design is completely digital allowing accurate control of the amplitude, frequency, and phase of all sinusoids making up the multi-tone signal. Simulations and FPGA experiments performed to date have verified the performance of the proposed design which is envisioned to open new directions in the mixed analog/digital testing field.","PeriodicalId":309921,"journal":{"name":"Proceedings., International Test Conference","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115979027","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 74
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