On achieving complete testability of synchronous sequential circuits with synchronizing sequences

Abstract

A completely testable circuit does not have any undetectable or redundant faults. We consider the problem of making synchronous sequential circuits that have synchronizing sequences completely testable for stuck-at faults. The method proposed is based on the removal of logic corresponding not only to redundant faults, but also to some undetectable yet irredundant faults. Thus, the proposed approach reduces the circuit size in addition to reducing or eliminating the extra hardware that may be otherwise necessary to render the circuit completely testable. A theoretical framework for achieving this goal was established earlier (1993). In this work, we give a detailed procedure based on the concepts of the previous work and give experimental results of its application.