Back annotation of physical defects into gate-level, realistic faults in digital ICs

IC complexity moves the design activity upwards, into higher levels of abstraction. Product quality requires the move of test activity downwards, down to IC physical level. High quality test requires the ability to cover physical defects. However, circuit complexity makes test preparation, at transistor level, prohibitive. A methodology for back annotation of physical defects into gate level realistic faults, is proposed in this paper. Bridging faults are selected, as they are the most likely faults in present-day process lines. It is shown that realistic faults, associated with routing patterns, can be used to represent the overall fault set, leading to an accurate evaluation of the defect level, used as the test quality indicator. A method to generate gate-level, realistic fault lists from the IC layout is presented, and is validated by simulation results.