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Proceedings., International Test Conference最新文献

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Generating march tests automatically 自动生成行军测试
Proceedings., International Test Conference Pub Date : 1994-10-02 DOI: 10.1109/TEST.1994.528034
A. V. Goor, B. Smit
{"title":"Generating march tests automatically","authors":"A. V. Goor, B. Smit","doi":"10.1109/TEST.1994.528034","DOIUrl":"https://doi.org/10.1109/TEST.1994.528034","url":null,"abstract":"Many memory tests have been designed in the past, one class of tests which has been proven to be very efficient in terms of fault coverage as well as test time, is the class of march tests. Designing march tests is a tedious, manual task. This paper presents a method which can, given a set of fault models, automatically generate the required march tests. It has been implemented in the programming language C and shown to be effective.","PeriodicalId":309921,"journal":{"name":"Proceedings., International Test Conference","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128791823","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 21
Control strategies for chip-based DFT/BIST hardware 基于芯片的DFT/BIST硬件控制策略
Proceedings., International Test Conference Pub Date : 1994-10-02 DOI: 10.1109/TEST.1994.528037
Debaditya Mukherjee, Massoud Pedram, M. Breuer
{"title":"Control strategies for chip-based DFT/BIST hardware","authors":"Debaditya Mukherjee, Massoud Pedram, M. Breuer","doi":"10.1109/TEST.1994.528037","DOIUrl":"https://doi.org/10.1109/TEST.1994.528037","url":null,"abstract":"We present strategies for controlling on-chip design-for-test (DFT) and built-in self-test (BIST) circuitry under a partially distributed test control architecture. These include mechanisms for broadcasting control information from apt integrated TAP controller over an infernal test bus, techniques for creating symbolic descriptions of local decoders that employ this information to control test resources, and algorithms for encoding the bus information. The encoding algorithms minimize a two-level implementation of the integrated TAP controller and/or the distributed decoders. These control strategies are IEEE 1149.1 boundary scan standard compliant and are applicable to both simple and complex DFT/BIST methodologies including those that employ multifunction and/or reconfigurable test registers and reconfigurable scan chains.","PeriodicalId":309921,"journal":{"name":"Proceedings., International Test Conference","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126269661","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A test methodology to support an ASEM MCM foundry 支持ASEM MCM铸造厂的测试方法
Proceedings., International Test Conference Pub Date : 1994-10-02 DOI: 10.1109/TEST.1994.527984
T. Storey, C. Lapihuska, E. Atwood, L. Su
{"title":"A test methodology to support an ASEM MCM foundry","authors":"T. Storey, C. Lapihuska, E. Atwood, L. Su","doi":"10.1109/TEST.1994.527984","DOIUrl":"https://doi.org/10.1109/TEST.1994.527984","url":null,"abstract":"MCM testing can be challenging enough when the chip, substrate, and MCM design are within the control of the same company. In the foundry environment, however, even more robust strategies must be adopted. In this paper a test methodology is described which consolidates the various MCM test stages to form a flexible, low-cost, quick turn-around-time test flow.","PeriodicalId":309921,"journal":{"name":"Proceedings., International Test Conference","volume":"102 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122028177","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Sequentially untestable faults identified without search ("simple implications beat exhaustive search!") 在不搜索的情况下识别出顺序不可测试的错误(“简单的暗示胜过详尽的搜索!”)
Proceedings., International Test Conference Pub Date : 1994-10-02 DOI: 10.1109/TEST.1994.527957
M. Iyer, M. Abramovici
{"title":"Sequentially untestable faults identified without search (\"simple implications beat exhaustive search!\")","authors":"M. Iyer, M. Abramovici","doi":"10.1109/TEST.1994.527957","DOIUrl":"https://doi.org/10.1109/TEST.1994.527957","url":null,"abstract":"This paper presents a novel fault-independent algorithm for identifying untestable faults in sequential circuits. The algorithm is based on a simple concept that a fault which requires an illegal combination of values as a necessary condition for its detection is untestable. It uses implications to find a subset of such faults whose detection requires conflicts on certain lines in the circuit. No global reset state is assumed and no state transition information is needed. Our fault-independent algorithm identifies untestable faults without any search as opposed to exhaustive search done by fault-oriented test generation algorithms. Results on benchmark and real circuits indicate that we find a large number of untestable faults, much faster (up to 3 orders of magnitude) than a test-generation-based algorithm that targeted the faults identified by our algorithm. Moreover, many faults identified as untestable by our approach were aborted when targeted by a sequential test generator.","PeriodicalId":309921,"journal":{"name":"Proceedings., International Test Conference","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126396449","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 34
A software architecture for mixed signal functional testing 混合信号功能测试的软件体系结构
Proceedings., International Test Conference Pub Date : 1994-10-02 DOI: 10.1109/TEST.1994.528002
John A. Masciola, Gerald K. Morgan, Geoffrey L. Templeton
{"title":"A software architecture for mixed signal functional testing","authors":"John A. Masciola, Gerald K. Morgan, Geoffrey L. Templeton","doi":"10.1109/TEST.1994.528002","DOIUrl":"https://doi.org/10.1109/TEST.1994.528002","url":null,"abstract":"Mixed signal functional board test has always posed a challenge for traditional ATE. The types of measurements required and the instrumentation needed to make these measurements vary widely. VXI-based solutions tend to provide a hardware solution, leaving the software as an exercise for the test engineer. A general purpose software environment that provides an application framework is also required. This paper describes the architecture of such a framework.","PeriodicalId":309921,"journal":{"name":"Proceedings., International Test Conference","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126715027","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Aliasing-free signature analysis for RAM BIST RAM BIST的无混叠签名分析
Proceedings., International Test Conference Pub Date : 1994-10-02 DOI: 10.1109/TEST.1994.527978
V. Yarmolik, M. Nicolaidis, O. Kebichi
{"title":"Aliasing-free signature analysis for RAM BIST","authors":"V. Yarmolik, M. Nicolaidis, O. Kebichi","doi":"10.1109/TEST.1994.527978","DOIUrl":"https://doi.org/10.1109/TEST.1994.527978","url":null,"abstract":"Signature analyzers are very efficient output response compactors in BIST techniques. The only limitation of signature analysis is the fault coverage reduction (aliasing) due to the information loss inherent to any data compaction. In this paper, in order to increase the effectiveness of RAM BIST, we fake advantage from the regularity of the RAM test algorithms and we show that aliasing-free signature analysis can be achieved in RAM BIST.","PeriodicalId":309921,"journal":{"name":"Proceedings., International Test Conference","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129422139","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
ECC-on-SIMM test challenges ECC-on-SIMM测试挑战
Proceedings., International Test Conference Pub Date : 1994-10-02 DOI: 10.1109/TEST.1994.527993
T. J. Dell
{"title":"ECC-on-SIMM test challenges","authors":"T. J. Dell","doi":"10.1109/TEST.1994.527993","DOIUrl":"https://doi.org/10.1109/TEST.1994.527993","url":null,"abstract":"The typical personal computer of today is used more and more to perform functions and run application programs that are critical to a business's success. One of the biggest problems that inhibits productivity in this environment Is the effect of a lock-up, crash or parity error caused by cosmic-ray radiation-induced soft errors in the DRAM chips. IBM has announced a family of plug-compatible, retrofittable SIMMs with built-in ECC to provide a solution to this problem. This paper addresses the challenges associated with the full functional test of a SIMM with on-board ECC using a very test-unfriendly industry-standard memory module interface.","PeriodicalId":309921,"journal":{"name":"Proceedings., International Test Conference","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133048409","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
In-system timing extraction and control through scan-based, test-access ports 系统内定时提取和控制通过扫描为基础，测试访问端口
Proceedings., International Test Conference Pub Date : 1994-10-02 DOI: 10.1109/TEST.1994.527969
A. DeHon
{"title":"In-system timing extraction and control through scan-based, test-access ports","authors":"A. DeHon","doi":"10.1109/TEST.1994.527969","DOIUrl":"https://doi.org/10.1109/TEST.1994.527969","url":null,"abstract":"We present circuits and techniques which allow the extraction of fine-grained timing information using a simple, scan-based, test-access port such as the JTAG/IEEE 1149 standard. We go on to show how these techniques can be combined with other simple circuits for post-fabrication timing control. These techniques open up opportunities to perform timing oriented tests through TAP control. Further, they allow in-system timing adaptation which can be exploited to achieve high system performance.","PeriodicalId":309921,"journal":{"name":"Proceedings., International Test Conference","volume":"16 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133227761","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Behavioral test generation using mixed integer nonlinear programming 使用混合整数非线性规划生成行为测试
Proceedings., International Test Conference Pub Date : 1994-10-02 DOI: 10.1109/TEST.1994.528045
R. Ramchandani, D. E. Thomas
{"title":"Behavioral test generation using mixed integer nonlinear programming","authors":"R. Ramchandani, D. E. Thomas","doi":"10.1109/TEST.1994.528045","DOIUrl":"https://doi.org/10.1109/TEST.1994.528045","url":null,"abstract":"This paper describes a novel technique to generate test vectors for single stuck-at faults using the behavioral description of the circuit function and the mapping from the behavior into the hardware that implements it. The test vector generation problem is formulated as a mixed integer nonlinear programming (MINLP) problem, and the test vectors are obtained by solving a series of MINLPs. The technique has been implemented and results from this approach show an order of magnitude speed up in test generation compared to existing gate-level sequential test generation tools.","PeriodicalId":309921,"journal":{"name":"Proceedings., International Test Conference","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133326274","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
Full symbolic ATPG for large circuits 用于大型电路的完整符号ATPG
Proceedings., International Test Conference Pub Date : 1994-10-02 DOI: 10.1109/TEST.1994.528047
G. Cabodi, P. Camurati, S. Quer
{"title":"Full symbolic ATPG for large circuits","authors":"G. Cabodi, P. Camurati, S. Quer","doi":"10.1109/TEST.1994.528047","DOIUrl":"https://doi.org/10.1109/TEST.1994.528047","url":null,"abstract":"Until now, symbolic FSM state space exploration techniques were limited to small circuits. This paper presents a combination of approximate forward and exact backward traversal that handles larger circuits. For the first time, we have been able to generate test patterns for or to tag as undetectable the faults of some ISCAS'89 and MCNC benchmarks never considered before.","PeriodicalId":309921,"journal":{"name":"Proceedings., International Test Conference","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132007954","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
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