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Proceedings., International Test Conference最新文献

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Using SCAN Bridge as an IEEE 1149.31 protocol addressable, multi-drop, backplane test bus 使用SCAN桥作为IEEE 1149.31协议可寻址，多滴，背板测试总线
Proceedings., International Test Conference Pub Date : 1994-10-02 DOI: 10.1109/TEST.1994.528053
J. Andrews
{"title":"Using SCAN Bridge as an IEEE 1149.31 protocol addressable, multi-drop, backplane test bus","authors":"J. Andrews","doi":"10.1109/TEST.1994.528053","DOIUrl":"https://doi.org/10.1109/TEST.1994.528053","url":null,"abstract":"National Semiconductor's SCAN Bridge is being used to provide an addressable, multi-drop, 1149.1-based backplane test bus. Its architecture is based upon defining two additional protocols to extend IEEE 1149.1 for use as a backplane test bus: an address protocol and a park protocol. These allow features such as the single, multicast, and broadcast address modes of P1149.5 to be included in the bridge.","PeriodicalId":309921,"journal":{"name":"Proceedings., International Test Conference","volume":"100 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132101942","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
An I/sub DDQ/ based built-in concurrent test technique for interconnects in a boundary scan environment 一种基于I/sub DDQ/的边界扫描环境互连内建并发测试技术
Proceedings., International Test Conference Pub Date : 1994-10-02 DOI: 10.1109/TEST.1994.528012
C. Su, Kychin Hwang, S. Jou
{"title":"An I/sub DDQ/ based built-in concurrent test technique for interconnects in a boundary scan environment","authors":"C. Su, Kychin Hwang, S. Jou","doi":"10.1109/TEST.1994.528012","DOIUrl":"https://doi.org/10.1109/TEST.1994.528012","url":null,"abstract":"An I/sub DDQ/ based scheme has been presented for concurrent built-in self-test of MCM interconnects. The scheme detects interconnect faults while the system is on-line.","PeriodicalId":309921,"journal":{"name":"Proceedings., International Test Conference","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131529314","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
An on-line data collection and analysis system for VLSI devices at wafer probe and final test 超大规模集成电路(VLSI)器件在晶圆探头和最终测试阶段的在线数据采集与分析系统
Proceedings., International Test Conference Pub Date : 1994-10-02 DOI: 10.1109/TEST.1994.528024
Gregory W. Papadeas, D. Gauthier
{"title":"An on-line data collection and analysis system for VLSI devices at wafer probe and final test","authors":"Gregory W. Papadeas, D. Gauthier","doi":"10.1109/TEST.1994.528024","DOIUrl":"https://doi.org/10.1109/TEST.1994.528024","url":null,"abstract":"This paper describes a flexible software system for the collection of parametric, functional pattern fail, and bitmap data on-line during production testing of VLSI devices. The data is automatically loaded into a relational database for subsequent analysis by process and yield improvement software. The user can control the type and amount of data that is collected at each stage of a product's life. By enabling data collection on every test, the same system can be used for engineering and debug analysis.","PeriodicalId":309921,"journal":{"name":"Proceedings., International Test Conference","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123859634","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
NAND trees accurately diagnose board-level pin faults NAND树准确诊断板级引脚故障
Proceedings., International Test Conference Pub Date : 1994-10-02 DOI: 10.1109/TEST.1994.528028
G. Robinson
{"title":"NAND trees accurately diagnose board-level pin faults","authors":"G. Robinson","doi":"10.1109/TEST.1994.528028","DOIUrl":"https://doi.org/10.1109/TEST.1994.528028","url":null,"abstract":"The NAND tree structures used in some semiconductor test methods have been used in board test environments as a simple test for open input and bidirectional pins. The test methods used at semiconductor test time have an unfortunate problem when used at board test: they give an incorrect diagnosis. A new test procedure is described that avoids this problem.","PeriodicalId":309921,"journal":{"name":"Proceedings., International Test Conference","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121273214","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A study of I/sub DDQ/ subset selection algorithms for bridging faults 桥接故障的I/sub DDQ/子集选择算法研究
Proceedings., International Test Conference Pub Date : 1994-10-02 DOI: 10.1109/TEST.1994.527982
S. Chakravarty, P. J. Thadikaran
{"title":"A study of I/sub DDQ/ subset selection algorithms for bridging faults","authors":"S. Chakravarty, P. J. Thadikaran","doi":"10.1109/TEST.1994.527982","DOIUrl":"https://doi.org/10.1109/TEST.1994.527982","url":null,"abstract":"Selecting a small subset of the set of functional vectors for performing I/sub DDQ/ measurement has previously been studied for leakage but not for bridging faults. Algorithms for this problem for all two line bridging faults, in combinational and sequential circuits, along with experimental results are presented.","PeriodicalId":309921,"journal":{"name":"Proceedings., International Test Conference","volume":"106 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121363865","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 21
Multi-frequency, multi-phase scan chain 多频、多相扫描链
Proceedings., International Test Conference Pub Date : 1994-10-02 DOI: 10.1109/TEST.1994.527966
Kee-sup Kim, Len Schultz
{"title":"Multi-frequency, multi-phase scan chain","authors":"Kee-sup Kim, Len Schultz","doi":"10.1109/TEST.1994.527966","DOIUrl":"https://doi.org/10.1109/TEST.1994.527966","url":null,"abstract":"The use multiple clocks presents an interesting problem to scan design. Traditionally, a separate scan chain has been provided for each clock, which results in longer than necessary scan operations due to unbalanced scan chain length. A set of methods that would allow mixing of memory elements clocked at different frequencies and phases in a single scan chain is presented and the proofs of the correct operation of the methods are given. If multiple scan chains are allowed, these methods make it possible to form scan chains of equivalent length for the savings in test application time and tester memory.","PeriodicalId":309921,"journal":{"name":"Proceedings., International Test Conference","volume":"156 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116054683","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A generic test and maintenance node for embedded system test 嵌入式系统测试的通用测试和维护节点
Proceedings., International Test Conference Pub Date : 1994-10-02 DOI: 10.1109/TEST.1994.528534
J. Lofgren
{"title":"A generic test and maintenance node for embedded system test","authors":"J. Lofgren","doi":"10.1109/TEST.1994.528534","DOIUrl":"https://doi.org/10.1109/TEST.1994.528534","url":null,"abstract":"In order to build high performance embedded test systems, a Digital Test and Maintenance ASIC (DTMA) with embedded microprocessor, test bus port, and test network communication ports has been conceived. This DTMA \"node\" and 2 companion analog data acquisition devices form the basis of a structured, system level design-for-test (DFT) methodology which is applicable to medium or high performance test and maintenance requirements. By offering a robust, minimal-parts-count solution, the methodology also reduces the non-recurring labor costs associated with DFT and the recurring costs of BIT hardware.","PeriodicalId":309921,"journal":{"name":"Proceedings., International Test Conference","volume":"589 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122846566","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
MicroSPARC: a case-study of scan based debug MicroSPARC:基于扫描的调试案例研究
Proceedings., International Test Conference Pub Date : 1994-10-02 DOI: 10.1109/TEST.1994.527937
K. Holdbrook, S. Joshi, Samir Mitra, J. Petolino, Renu Raman, M. Wong
{"title":"MicroSPARC: a case-study of scan based debug","authors":"K. Holdbrook, S. Joshi, Samir Mitra, J. Petolino, Renu Raman, M. Wong","doi":"10.1109/TEST.1994.527937","DOIUrl":"https://doi.org/10.1109/TEST.1994.527937","url":null,"abstract":"MicroSPARC is a highly integrated, high volume, low-cost CMOS RISC microprocessor. To meet the design goals, it included fully synchronous logic with full testability support, using scannable flops and a JTAG-compliant clock controller. This paper describes the key features of the scan design and how they were used to maximize parallelism in system and tester environments, while reducing bottlenecks in functional and timing debug. The paper concludes with a discussion of lessons learned. A related paper (1994) describes the methodologies used and benefits realized in the tester environment, along with data collected during the debug phase of the project.","PeriodicalId":309921,"journal":{"name":"Proceedings., International Test Conference","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127191522","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 45
Balancing structured and ad-hoc design for test: testing of the PowerPC 603 microprocessor 平衡测试的结构化和临时设计:powerpc603微处理器的测试
Proceedings., International Test Conference Pub Date : 1994-10-02 DOI: 10.1109/TEST.1994.527938
C. Hunter, E. K. Vida-Torku, J. LeBlanc
{"title":"Balancing structured and ad-hoc design for test: testing of the PowerPC 603 microprocessor","authors":"C. Hunter, E. K. Vida-Torku, J. LeBlanc","doi":"10.1109/TEST.1994.527938","DOIUrl":"https://doi.org/10.1109/TEST.1994.527938","url":null,"abstract":"The PowerPC 603 microprocessor is a high performance, low power, and low cost RISC microprocessor which was designed at the Somerset Design Center by a team of Motorola, IBM and Apple engineers. The testability and manufacturability features implemented in the PowerPC 603 microprocessor are presented, as well as the issues involved in reconciling a common test plan for two fabrication facilities with differing expectations.","PeriodicalId":309921,"journal":{"name":"Proceedings., International Test Conference","volume":"76 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127425843","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 33
Fault injection boundary scan design for verification of fault tolerant systems 容错系统验证的故障注入边界扫描设计
Proceedings., International Test Conference Pub Date : 1994-10-02 DOI: 10.1109/TEST.1994.528013
S. Chau
{"title":"Fault injection boundary scan design for verification of fault tolerant systems","authors":"S. Chau","doi":"10.1109/TEST.1994.528013","DOIUrl":"https://doi.org/10.1109/TEST.1994.528013","url":null,"abstract":"In this paper, we propose a design technique called the Fault Injection Boundary Scan (FIBS) for fault injection that is much more efficient than the traditional hardwired pin-level fault injection. The FIBS augments the boundary scan design to facilitate the injection of faults to the input and output pins of a VLSI chip. In addition to the capabilities of a conventional boundary scan design, the FIBS can interpret the test vector contained in the boundary scan cells as markers for fault-injected pins during fault injection. The compatibility of the FIBS with the boundary scan also promises relatively small overhead.","PeriodicalId":309921,"journal":{"name":"Proceedings., International Test Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128444093","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 19
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