A generic test and maintenance node for embedded system test

Abstract

In order to build high performance embedded test systems, a Digital Test and Maintenance ASIC (DTMA) with embedded microprocessor, test bus port, and test network communication ports has been conceived. This DTMA "node" and 2 companion analog data acquisition devices form the basis of a structured, system level design-for-test (DFT) methodology which is applicable to medium or high performance test and maintenance requirements. By offering a robust, minimal-parts-count solution, the methodology also reduces the non-recurring labor costs associated with DFT and the recurring costs of BIT hardware.