平衡测试的结构化和临时设计:powerpc603微处理器的测试

Proceedings., International Test Conference Pub Date : 1994-10-02 DOI:10.1109/TEST.1994.527938

C. Hunter, E. K. Vida-Torku, J. LeBlanc

{"title":"平衡测试的结构化和临时设计:powerpc603微处理器的测试","authors":"C. Hunter, E. K. Vida-Torku, J. LeBlanc","doi":"10.1109/TEST.1994.527938","DOIUrl":null,"url":null,"abstract":"The PowerPC 603 microprocessor is a high performance, low power, and low cost RISC microprocessor which was designed at the Somerset Design Center by a team of Motorola, IBM and Apple engineers. The testability and manufacturability features implemented in the PowerPC 603 microprocessor are presented, as well as the issues involved in reconciling a common test plan for two fabrication facilities with differing expectations.","PeriodicalId":309921,"journal":{"name":"Proceedings., International Test Conference","volume":"76 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1994-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"33","resultStr":"{\"title\":\"Balancing structured and ad-hoc design for test: testing of the PowerPC 603 microprocessor\",\"authors\":\"C. Hunter, E. K. Vida-Torku, J. LeBlanc\",\"doi\":\"10.1109/TEST.1994.527938\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The PowerPC 603 microprocessor is a high performance, low power, and low cost RISC microprocessor which was designed at the Somerset Design Center by a team of Motorola, IBM and Apple engineers. The testability and manufacturability features implemented in the PowerPC 603 microprocessor are presented, as well as the issues involved in reconciling a common test plan for two fabrication facilities with differing expectations.\",\"PeriodicalId\":309921,\"journal\":{\"name\":\"Proceedings., International Test Conference\",\"volume\":\"76 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1994-10-02\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"33\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings., International Test Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/TEST.1994.527938\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings., International Test Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/TEST.1994.527938","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 33

摘要

PowerPC 603微处理器是一款高性能、低功耗、低成本的RISC微处理器，由摩托罗拉、IBM和苹果的工程师团队在萨默塞特设计中心设计。介绍了在PowerPC 603微处理器中实现的可测试性和可制造性特性，以及调和两个具有不同期望的制造设施的公共测试计划所涉及的问题。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

查看原文本刊更多论文

Balancing structured and ad-hoc design for test: testing of the PowerPC 603 microprocessor

The PowerPC 603 microprocessor is a high performance, low power, and low cost RISC microprocessor which was designed at the Somerset Design Center by a team of Motorola, IBM and Apple engineers. The testability and manufacturability features implemented in the PowerPC 603 microprocessor are presented, as well as the issues involved in reconciling a common test plan for two fabrication facilities with differing expectations.

求助全文

通过发布文献求助，成功后即可免费获取论文全文。去求助

来源期刊

Proceedings., International Test Conference

自引率

0.00%

发文量