{"title":"ATPG for heat dissipation minimization during test application","authors":"Seongmoon Wang, S. Gupta","doi":"10.1109/TEST.1994.527956","DOIUrl":"https://doi.org/10.1109/TEST.1994.527956","url":null,"abstract":"A new ATPG algorithm has been proposed that reduces average heat dissipation (between successive test vectors) during test application. The objective is to permit safe and inexpensive testing of low power circuits and bare dies that would otherwise require expensive heat removal equipment for testing at high speeds. Three new functions, namely transition controllability, observability and test generation costs, have been defined. It has been shown that the transition test generation cost is the minimum number of transitions required to test the corresponding stuck-at fault in fanout free circuits. This cost function is used for target fault selection while the other two functions are used to guide the backtrace and objective selection procedures of PODEM. The tests generated by the proposed ATPG decrease heat dissipation during test application by a factor of 2-23 for benchmark circuits.","PeriodicalId":309921,"journal":{"name":"Proceedings., International Test Conference","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128177281","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Structure and metrology for a single-wire analog testability bus","authors":"Yunsheng Lu, W. Mao, R. Dandapani, R. K. Gulati","doi":"10.1109/TEST.1994.528041","DOIUrl":"https://doi.org/10.1109/TEST.1994.528041","url":null,"abstract":"A structure for testing the interconnect faults and measurement of discrete components on mixed-signal boards is proposed. The structure requires one analog pin in addition to the IEEE 1149.1 pins on each mixed-signal IC. Simulation results are provided to show the accuracy of the metrology.","PeriodicalId":309921,"journal":{"name":"Proceedings., International Test Conference","volume":"22 2","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113977180","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Is I/sub DDQ/ yield loss inevitable?","authors":"S. Davidson","doi":"10.1109/TEST.1994.528001","DOIUrl":"https://doi.org/10.1109/TEST.1994.528001","url":null,"abstract":"I/sub DDQ/ testing is a powerful way to improve the quality of low fault coverage tests, and to detect defects that are hard or impossible to detect using traditional voltage testing methods. However, it appears that there is some yield loss associated with I/sub DDQ/ testing, where yield loss means that devices passing burn-in and system tests fail I/sub DDQ/ test. This paper gives reasons why such yield loss is inevitable, and must be considered when making a decision whether or not to use I/sub DDQ/ testing. We also present some evidence backing up this speculation, and a brief economic model to help in making I/sub DDQ/ testing decisions.","PeriodicalId":309921,"journal":{"name":"Proceedings., International Test Conference","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114456312","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Ultra hi-speed pin-electronics and test station using GaAs IC","authors":"T. Sekino, T. Okayasu","doi":"10.1109/TEST.1994.528014","DOIUrl":"https://doi.org/10.1109/TEST.1994.528014","url":null,"abstract":"This paper describes the pin-electronics technique applied in a high speed/high pin count test head which targets testing quarter micron high speed CMOS VLSI devices. The pin-electronics operate up to 1 GHz with the following characteristics; timing error<20 ps, rise/fall time<200 ps, minimum pulse width<500 ps, output voltage range -2.0 V to 3.5 V and output voltage amplitude =3.5 V. This was achieved by reducing to 1/5 the GaAs specific problem of changing gain in the low frequency range. The pin-electronics were implemented as a Driver Comparator Multichip Module in order to achieve a high pin count test head (1280 pins max).","PeriodicalId":309921,"journal":{"name":"Proceedings., International Test Conference","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128796411","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A test process optimization and cost modeling tool","authors":"T. Moore","doi":"10.1109/TEST.1994.527941","DOIUrl":"https://doi.org/10.1109/TEST.1994.527941","url":null,"abstract":"This paper will describe a test process modeling tool developed by Digital Equipment Corporation in Maynard Mass. to be used by design and manufacturing process engineering to determine the most economic test process without sacrificing test coverage or yield. The test cost modeling tool can be used to understand the behavior of the test process and determine how to reduce the impact of test upon the total module manufacturing cost. This paper discusses the test process modeling tool and how it can be used to eliminate test process steps and optimize the test process.","PeriodicalId":309921,"journal":{"name":"Proceedings., International Test Conference","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128366869","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A hybrid fault simulator for synchronous sequential circuits","authors":"Rolf Krieger, B. Becker, Martin Keim","doi":"10.1109/TEST.1994.528006","DOIUrl":"https://doi.org/10.1109/TEST.1994.528006","url":null,"abstract":"Fault simulation for synchronous sequential circuits is a very time-consuming task. The complexity of the task increases if there is no information available about the initial state of the circuit. In this case, an unknown initial state is assumed which is usually handled by introducing a three-valued logic. It is known that fault simulation based upon this logic only determines a lower bound for the fault coverage achieved by a test sequence. Therefore, we developed a hybrid fault simulator H-FS combining the advantages of a fault simulator using the three-valued logic and of an exact symbolic fault simulator based upon binary decision diagrams. H-FS is able to handle even the largest benchmark circuits and thereby determines fault coverages much more accurately than previous algorithms using the three-valued logic.","PeriodicalId":309921,"journal":{"name":"Proceedings., International Test Conference","volume":"487 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120998537","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Design of an efficient weighted random pattern generation system","authors":"R. Kapur, S. Patil, T. Snethen, T. Williams","doi":"10.1109/TEST.1994.527991","DOIUrl":"https://doi.org/10.1109/TEST.1994.527991","url":null,"abstract":"This paper describes the design of an efficient weighted random pattern system. The performance of the system is measured by the number of weight sets and the number of weighted random patterns required for high fault coverage. Various heuristics that affect the performance of the system are discussed and an experimental evaluation is provided.","PeriodicalId":309921,"journal":{"name":"Proceedings., International Test Conference","volume":"369 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122986546","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"When does it make C to give up physical test access?","authors":"David A. Greene","doi":"10.1109/TEST.1994.527942","DOIUrl":"https://doi.org/10.1109/TEST.1994.527942","url":null,"abstract":"As conventional board designs continue to decrease in size, the cost of \"test\" is rising proportionally relative to physical, bed-of-nails access. The purpose of this paper is to provide a generalized framework by which users can more quantitatively analyze the costs and benefits of removing physical test access from conventional, surface mount technology (SMT) boards for the purpose of bed-of-nails testing.","PeriodicalId":309921,"journal":{"name":"Proceedings., International Test Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126322468","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Variable supply voltage testing for analogue CMOS and bipolar circuits","authors":"E. Bruls","doi":"10.1109/TEST.1994.528000","DOIUrl":"https://doi.org/10.1109/TEST.1994.528000","url":null,"abstract":"In this paper a test technique based on the application of power supply levels outside the specified operational range is evaluated with respect to the detection of realistic defects. This work is motivated by two problems encountered in the production test environment. First of all, the test development for analogue circuits is mainly specification driven and as such cannot guarantee a certain fault coverage or quality. Secondly, testing the performance of a state-of-the-art analogue circuit may require application of high performance stimuli (e.g. with respect to frequency or Signal-to-Noise Ratio), while the integrity of such signals is difficult to guarantee because of the non-ideal interface. Two analogue circuits, a CMOS and a bipolar device, are used to evaluate this test technique by means of simulations and to verify it as much as possible by means of measurements.","PeriodicalId":309921,"journal":{"name":"Proceedings., International Test Conference","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127443587","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Configuring flip-flops to BIST registers","authors":"A. P. Stroele, H. Wunderlich","doi":"10.1109/TEST.1994.528043","DOIUrl":"https://doi.org/10.1109/TEST.1994.528043","url":null,"abstract":"Built-in self-test test registers must segment a circuit such that there exists a feasible test schedule. If a register transfer description is used for selecting the positions of test registers, the space for optimizations is small. In this paper, 1-bit test cells are inserted at gate level, and an initial test schedule is constructed. Based on the information of this schedule, test cells that can be controlled in the same way are assembled to test registers. Finally, a test schedule at RT level is constructed and a minimal set of test control signals is determined. The presented approach can reduce both BIST hardware overhead and test application time. It is applicable to control units and circuits produced by control oriented synthesis where an RT description is not available. Considerable gains can also be obtained if existing RT structures are reconfigured for self-testing in the described way.","PeriodicalId":309921,"journal":{"name":"Proceedings., International Test Conference","volume":"463 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131778225","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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