Structure and metrology for a single-wire analog testability bus

Proceedings., International Test Conference Pub Date : 1994-10-02 DOI:10.1109/TEST.1994.528041

Yunsheng Lu, W. Mao, R. Dandapani, R. K. Gulati

引用次数: 21

Abstract

A structure for testing the interconnect faults and measurement of discrete components on mixed-signal boards is proposed. The structure requires one analog pin in addition to the IEEE 1149.1 pins on each mixed-signal IC. Simulation results are provided to show the accuracy of the metrology.

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单线模拟测试总线的结构与计量

提出了一种用于混合信号板互连故障检测和离散元件测量的结构。该结构除了每个混合信号IC上的IEEE 1149.1引脚外，还需要一个模拟引脚。仿真结果显示了计量的准确性。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Proceedings., International Test Conference

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