MicroSPARC: a case-study of scan based debug

MicroSPARC is a highly integrated, high volume, low-cost CMOS RISC microprocessor. To meet the design goals, it included fully synchronous logic with full testability support, using scannable flops and a JTAG-compliant clock controller. This paper describes the key features of the scan design and how they were used to maximize parallelism in system and tester environments, while reducing bottlenecks in functional and timing debug. The paper concludes with a discussion of lessons learned. A related paper (1994) describes the methodologies used and benefits realized in the tester environment, along with data collected during the debug phase of the project.