Proceedings., International Test Conference最新文献

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On synthesizing circuits with implicit testability constraints 具有隐式可测性约束的合成电路
Proceedings., International Test Conference Pub Date : 1994-10-02 DOI: 10.1109/TEST.1994.528048
H. Cox
{"title":"On synthesizing circuits with implicit testability constraints","authors":"H. Cox","doi":"10.1109/TEST.1994.528048","DOIUrl":"https://doi.org/10.1109/TEST.1994.528048","url":null,"abstract":"The goal of test synthesis is to create a circuit which is completely testable under a design-for-test (DFT) methodology while meeting performance and area requirements. It includes such steps as testability design rule checking and automated repair of identified violations. Potential violations include clock and asynchronous circuitry which do not operate in a manner consistent with the chosen methodology and tools. Repair is performed by transforming the network through the insertion of additional logic to perform test functions (a scan chain, for example) and mapping this logic into the implementation technology, without affecting the original, system mode operation of the network. This paper discusses the concept of test synthesis constraints which embody the conditions under which the circuit must operate in order to be fully testable. Based on the constraints, the circuit is transformed using algorithms similar to those of automatic test pattern generation. Rather than adding entirely new hardware, existing system logic and connectivity is used to implement test functions wherever possible. Results produced by a prototype implementation indicate that test logic can be inserted into a network with very little performance or area overhead.","PeriodicalId":309921,"journal":{"name":"Proceedings., International Test Conference","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116775868","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 21
3B21D BIST/Boundary-Scan system diagnostic test story 3B21D BIST/边界扫描系统诊断测试故事
Proceedings., International Test Conference Pub Date : 1994-10-02 DOI: 10.1109/TEST.1994.527943
Edward C. Behnke
{"title":"3B21D BIST/Boundary-Scan system diagnostic test story","authors":"Edward C. Behnke","doi":"10.1109/TEST.1994.527943","DOIUrl":"https://doi.org/10.1109/TEST.1994.527943","url":null,"abstract":"The 3B21D BIST and Boundary-Scan Design, based on the ANSI/IEEE Std 1149.1-1990, has given the 3B21D System Diagnostic Test Strategy an excellent set of tests at all levels of product assembly.","PeriodicalId":309921,"journal":{"name":"Proceedings., International Test Conference","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115479643","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Environmental Stress Testing with Boundary-Scan 边界扫描环境压力测试
Proceedings., International Test Conference Pub Date : 1994-10-02 DOI: 10.1109/TEST.1994.527964
D. Le, Ivan Karolik, Ronald Smith, A. Mcgovern, Chyral Curette, Joseph Ulbin, Michael Zarubaiko, Charles Henry, L. Stevens
{"title":"Environmental Stress Testing with Boundary-Scan","authors":"D. Le, Ivan Karolik, Ronald Smith, A. Mcgovern, Chyral Curette, Joseph Ulbin, Michael Zarubaiko, Charles Henry, L. Stevens","doi":"10.1109/TEST.1994.527964","DOIUrl":"https://doi.org/10.1109/TEST.1994.527964","url":null,"abstract":"Environmental Stress Testing (EST) enhances product quality and reliability by detecting latent or marginal defects in a product. For EST to be effective, testing of a product must achieve a high fault coverage so that as many EST-induced defects can be detected. By utilizing Boundary-Scan (IEEE Std 1149.1-1990), EST can achieve a high fault coverage and at the same time, minimize test cost. The paper describes a complete infrastructure, both software and hardware, for using Boundary-Scan (B-S) in EST. In addition, the paper shows a simplified control mechanism to select individual circuit packs for Boundary-Scan testing. This control mechanism minimizes the number of wires required to drive the control interface and thus, the number of wires in the cable that connects a tester to the backplane of a system under test and across which Boundary-Scan tests are executed. Finally, the paper presents and discusses some study results for evaluating the effectiveness of monitored EST.","PeriodicalId":309921,"journal":{"name":"Proceedings., International Test Conference","volume":"82 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114325533","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Implementation of a dual segment architecture for a high pin count VLSI test system 高引脚数VLSI测试系统双段架构的实现
Proceedings., International Test Conference Pub Date : 1994-10-02 DOI: 10.1109/TEST.1994.527958
M.G. Davis
{"title":"Implementation of a dual segment architecture for a high pin count VLSI test system","authors":"M.G. Davis","doi":"10.1109/TEST.1994.527958","DOIUrl":"https://doi.org/10.1109/TEST.1994.527958","url":null,"abstract":"This paper describes a dual segment VLSI test system architecture. It describes the design and cost goals that led us to this architecture. It also describes the direct and indirect benefits of this architecture.","PeriodicalId":309921,"journal":{"name":"Proceedings., International Test Conference","volume":"263 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114470672","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Development of a solution for achieving known-good-die 开发一个解决方案来实现已知的好模具
Proceedings., International Test Conference Pub Date : 1994-10-02 DOI: 10.1109/TEST.1994.527931
L. Prokopchak
{"title":"Development of a solution for achieving known-good-die","authors":"L. Prokopchak","doi":"10.1109/TEST.1994.527931","DOIUrl":"https://doi.org/10.1109/TEST.1994.527931","url":null,"abstract":"A major problem curtailing the growth of the multichip module market is the IC manufacturer's inability to provide known-good-die. To address this, a cost-effective process to burn-in and test at the die level is in development.","PeriodicalId":309921,"journal":{"name":"Proceedings., International Test Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116148704","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Testing issues on high speed synchronous DRAMs 高速同步dram的测试问题
Proceedings., International Test Conference Pub Date : 1994-10-02 DOI: 10.1109/TEST.1994.527973
Wha-Joon Lee
{"title":"Testing issues on high speed synchronous DRAMs","authors":"Wha-Joon Lee","doi":"10.1109/TEST.1994.527973","DOIUrl":"https://doi.org/10.1109/TEST.1994.527973","url":null,"abstract":"The test programming becomes very much complicated due to functionality and special features implemented in SDRAMs. Considering the combination of speed variations and operational modes, the number of the test items would easily exceed beyond the acceptable limit. The SDRAM testing issues are listed as follows: high speed tests with a slow production tester; load board and load circuit design for high speed testing; and test program development for the new features.","PeriodicalId":309921,"journal":{"name":"Proceedings., International Test Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122747240","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Testability features of the MC68060 microprocessor MC68060微处理器的可测试性特点
Proceedings., International Test Conference Pub Date : 1994-10-02 DOI: 10.1109/TEST.1994.527936
A. Crouch, Matthew Pressly, J. Circello
{"title":"Testability features of the MC68060 microprocessor","authors":"A. Crouch, Matthew Pressly, J. Circello","doi":"10.1109/TEST.1994.527936","DOIUrl":"https://doi.org/10.1109/TEST.1994.527936","url":null,"abstract":"This report describes the testability design goals, constraints, and strategies used in the development of the MC68060 microprocessor. It explores the design choices that were made and the considerations that led to those choices. It presents the architectures and methodologies used to implement the design choices, and ends by describing the successes, failures, and future refinements of the test methodologies and architectures.","PeriodicalId":309921,"journal":{"name":"Proceedings., International Test Conference","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131691651","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 33
Hybrid design for testability combining scan and clock line control and method for test generation 扫描与时钟线控制相结合的可测性混合设计与测试生成方法
Proceedings., International Test Conference Pub Date : 1994-10-02 DOI: 10.1109/TEST.1994.527968
S. Baeg, W. A. Rogers
{"title":"Hybrid design for testability combining scan and clock line control and method for test generation","authors":"S. Baeg, W. A. Rogers","doi":"10.1109/TEST.1994.527968","DOIUrl":"https://doi.org/10.1109/TEST.1994.527968","url":null,"abstract":"A hybrid DFT method is proposed to reduce the hardware penalty of traditional DFT methods and test generation time. It takes advantages of both traditional DFT methods like scan and DFT methods which control clocks for testability. The hardware scheme and test generation algorithm are presented. Test generation results for ISCAS '89 circuits have been generated and showed an improvement in test generation time and fault coverage.","PeriodicalId":309921,"journal":{"name":"Proceedings., International Test Conference","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134481607","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Application of optoelectronic techniques to high speed testing 光电技术在高速测试中的应用
Proceedings., International Test Conference Pub Date : 1994-10-02 DOI: 10.1109/TEST.1994.528017
E. Sokolowska, B. Kaminska
{"title":"Application of optoelectronic techniques to high speed testing","authors":"E. Sokolowska, B. Kaminska","doi":"10.1109/TEST.1994.528017","DOIUrl":"https://doi.org/10.1109/TEST.1994.528017","url":null,"abstract":"The concept and experimental results for the novel optoelectronic architecture of the IC tester allowing very high test rates is presented. This architecture is based on our new alternative approach of encoding the data implying double optical pulses. The validity of the concept has been confirmed with the simulation results. This new method along with optical multiplexing and self-clocked optical distribution resulted in outstanding performance and revealed numerous possibilities for the proposed architecture.","PeriodicalId":309921,"journal":{"name":"Proceedings., International Test Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130948846","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
On the initialization of sequential circuits 关于顺序电路的初始化
Proceedings., International Test Conference Pub Date : 1994-10-02 DOI: 10.1109/TEST.1994.527954
J. Wehbeh, D. Saab
{"title":"On the initialization of sequential circuits","authors":"J. Wehbeh, D. Saab","doi":"10.1109/TEST.1994.527954","DOIUrl":"https://doi.org/10.1109/TEST.1994.527954","url":null,"abstract":"A general method for determining whether a certain design is initializable, and for generating its initialization sequence, is presented. This method is based on structural decomposition of the circuit, and can handle both logical (using X-value simulation) and functional initializabilities. Results for some benchmark circuits are also presented.","PeriodicalId":309921,"journal":{"name":"Proceedings., International Test Conference","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130965821","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 37
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