{"title":"一种在高速测试过程中减少传输线影响的测试系统架构","authors":"Marc Mydill","doi":"10.1109/TEST.1994.528016","DOIUrl":null,"url":null,"abstract":"Testing high speed CMOS devices in a \"non-terminated\" transmission line environment can result in significant timing errors due to signal reflections. These errors can be substantially reduced with a test system designed to minimize the distance between device outputs and tester comparator inputs.","PeriodicalId":309921,"journal":{"name":"Proceedings., International Test Conference","volume":"25 10 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1994-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"10","resultStr":"{\"title\":\"A test system architecture to reduce transmission line effects during high speed testing\",\"authors\":\"Marc Mydill\",\"doi\":\"10.1109/TEST.1994.528016\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Testing high speed CMOS devices in a \\\"non-terminated\\\" transmission line environment can result in significant timing errors due to signal reflections. These errors can be substantially reduced with a test system designed to minimize the distance between device outputs and tester comparator inputs.\",\"PeriodicalId\":309921,\"journal\":{\"name\":\"Proceedings., International Test Conference\",\"volume\":\"25 10 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1994-10-02\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"10\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings., International Test Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/TEST.1994.528016\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings., International Test Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/TEST.1994.528016","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A test system architecture to reduce transmission line effects during high speed testing
Testing high speed CMOS devices in a "non-terminated" transmission line environment can result in significant timing errors due to signal reflections. These errors can be substantially reduced with a test system designed to minimize the distance between device outputs and tester comparator inputs.
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