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Interface-based design of systems-on-chip using UML-RT 基于UML-RT的片上系统接口设计
4th IEEE International Workshop on System-on-Chip for Real-Time Applications Pub Date : 2004-07-19 DOI: 10.1109/IWSOC.2004.1319846
A. Chureau, Y. Savaria, E. Aboulhamid
{"title":"Interface-based design of systems-on-chip using UML-RT","authors":"A. Chureau, Y. Savaria, E. Aboulhamid","doi":"10.1109/IWSOC.2004.1319846","DOIUrl":"https://doi.org/10.1109/IWSOC.2004.1319846","url":null,"abstract":"While the IC industry tries to harness system-on-chip complexity by reusing intellectual property modules, practical problems abound, reusing within tight hardware constraints is a design journey that may cost more than building from scratch. Platforms using pre-characterized interfaces gained acceptance as a paradigm that increases reuse predictability. In this paper, we present an interface-based approach to SoC design based on contract adorned UML-RT capsules. It is shown that well defined interfaces are the key to define a systematic path towards the implementation of a system-on-chip model. Two sets of capsules that form the vase of two platforms, one for packet based video processing and one for software radio, are built. IP reuse, refinement and profiling are performed within the context of these two platforms.","PeriodicalId":306688,"journal":{"name":"4th IEEE International Workshop on System-on-Chip for Real-Time Applications","volume":"72 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-07-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123471039","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
An efficient VLSI implementation of MC interpolation for MPEG-4 MPEG-4中MC插值的高效VLSI实现
4th IEEE International Workshop on System-on-Chip for Real-Time Applications Pub Date : 2004-07-19 DOI: 10.1109/IWSOC.2004.1319868
Deng Lei, Wen Gao, Mingzeng Hu, Z. Ji
{"title":"An efficient VLSI implementation of MC interpolation for MPEG-4","authors":"Deng Lei, Wen Gao, Mingzeng Hu, Z. Ji","doi":"10.1109/IWSOC.2004.1319868","DOIUrl":"https://doi.org/10.1109/IWSOC.2004.1319868","url":null,"abstract":"Quarter sample mode interpolation is one of critical paths of the MPEG-4 decoder because it has a finite impulse response (FIR) digital filter which is a computationally expensive process. Normal FIR architectures are not suitable for this application due to the set of short input data streams. After reforming a referenced pure systolic FIR, the paper gets an efficient architecture of quarter sample mode interpolation and the architecture is suitable for VLSI. Experimental result shows that the proposed architecture can satisfy MPEG-4 decoder applications.","PeriodicalId":306688,"journal":{"name":"4th IEEE International Workshop on System-on-Chip for Real-Time Applications","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-07-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123695810","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A CMOS high-voltage DC-DC up converter dedicated for ultrasonic applications 一种用于超声波应用的CMOS高压DC-DC上变频器
4th IEEE International Workshop on System-on-Chip for Real-Time Applications Pub Date : 2004-07-19 DOI: 10.1109/IWSOC.2004.1319862
R. Chebli, M. Sawan
{"title":"A CMOS high-voltage DC-DC up converter dedicated for ultrasonic applications","authors":"R. Chebli, M. Sawan","doi":"10.1109/IWSOC.2004.1319862","DOIUrl":"https://doi.org/10.1109/IWSOC.2004.1319862","url":null,"abstract":"This paper concerns the design and implementation of a fully integrated high voltage CMOS DC-DC up converter (VHVUC) dedicated to ultrasonic transmitters. This VHVUC new topology, followed by a drive amplifier, is based on a multiple-stage charge pump circuit and a level-up shifter is used in each stage as a clock generator in order to increase exponentially the DC voltage. A drive amplifier, based on a level-up stage and a class D switching output stage. It is used to excite the ultrasonic transducer, resonate at 3.5 MHz. Simulation results of the proposed converter, using a 0.8/spl mu/m CMOS/DMOS High-Voltage process technology, show output voltage of 200 V with 83% gain voltage factor and a 95 mV output ripples for 2 MHz frequency. Also, the drive amplifier for single shock excitation show a 140 V spike at the transducer element with a pulse repetition time of 260 /spl mu/s and a rise and fall times of 220 ns and 713 ns respectively with a peak current through the transducer element of 25 mA. These results show the feasibility of applying HV process technology to replace conventional electronic transmitter technology.","PeriodicalId":306688,"journal":{"name":"4th IEEE International Workshop on System-on-Chip for Real-Time Applications","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-07-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125879711","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
Formal verification of digital circuits 数字电路的正式验证
4th IEEE International Workshop on System-on-Chip for Real-Time Applications Pub Date : 2004-07-19 DOI: 10.1109/IWSOC.2004.10004
A. Salem
{"title":"Formal verification of digital circuits","authors":"A. Salem","doi":"10.1109/IWSOC.2004.10004","DOIUrl":"https://doi.org/10.1109/IWSOC.2004.10004","url":null,"abstract":"For more than two decades formal verification of digital circuits is a hot research topic and in the last ten years this technology finds its way in the industry where EDA companies have produced a number of efficient tools. This tutorial covers the various techniques used to verify the correctness of combinational and sequential circuits. Also, the verification of properties using model checking will be discussed. The topics covered in the tutorial are: HDL based verification, Binary Decision Diagrams (BDD), SAT solvers, Theorem provers, Combinational Equivalence Checkers, Miter Circuit, SAT / BDD partitioning, Finite State Machine traversal algorithms, Model Checking.","PeriodicalId":306688,"journal":{"name":"4th IEEE International Workshop on System-on-Chip for Real-Time Applications","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-07-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128706441","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
SoC features for a multi-processor WCDMA base-station modem SoC功能用于多处理器WCDMA基站调制解调器
4th IEEE International Workshop on System-on-Chip for Real-Time Applications Pub Date : 2004-07-19 DOI: 10.1109/IWSOC.2004.1319901
R. Hobson, Allan R. Dyck, K. Cheung
{"title":"SoC features for a multi-processor WCDMA base-station modem","authors":"R. Hobson, Allan R. Dyck, K. Cheung","doi":"10.1109/IWSOC.2004.1319901","DOIUrl":"https://doi.org/10.1109/IWSOC.2004.1319901","url":null,"abstract":"WCDMA is a demanding 3rd generation wireless air interface technique. This paper discusses some system-on-chip architectural features associated with a fine-medium grain parallel DSP-based processor implementation of the base-band receiver section of a frequency division duplex WCDMA base-station. The software-oriented techniques are also relevant to other applications which require dense DSP.","PeriodicalId":306688,"journal":{"name":"4th IEEE International Workshop on System-on-Chip for Real-Time Applications","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-07-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121537042","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Silicon modeling of nanometer systems-on-chip 纳米片上系统的硅建模
4th IEEE International Workshop on System-on-Chip for Real-Time Applications Pub Date : 2004-07-19 DOI: 10.1109/IWSOC.2004.59
C. Robertson
{"title":"Silicon modeling of nanometer systems-on-chip","authors":"C. Robertson","doi":"10.1109/IWSOC.2004.59","DOIUrl":"https://doi.org/10.1109/IWSOC.2004.59","url":null,"abstract":"Given that more than half of mixed signal designs are failing first silicon, SoC designs require a comprehensive approach to parasitic extraction that satisfies the needs for accuracy, performance and detailed analysis. Parasitic extraction tools need to provide not only comprehensive evidence of unintentional parasitic effects, but also accurate data for accurate analysis. These analysis requirements may include: static timing (C or RC) for traditional timing analysis and overall net delay; dynamic timing (C or CRC) for propagation delay with all circuitry active; Noise (RC) for crosstalk and signal integrity issues; Power (R) for IR drop and hotspots; and reliability (R) for yield analysis and electromigration. The design styles found in SoCs, be they analog, memory or full custom, etc., require a comprehensive approach to extraction. Designers need an LVS parasitic extraction tool suite that provides gate-level, transistor level, and mixed-level analysis, plus accuracy, capacity and performance across all design styles to obtain accurate silicon modeling.","PeriodicalId":306688,"journal":{"name":"4th IEEE International Workshop on System-on-Chip for Real-Time Applications","volume":"156 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-07-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121724926","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Network on chip simulations for benchmarking 网络芯片模拟基准测试
4th IEEE International Workshop on System-on-Chip for Real-Time Applications Pub Date : 2004-07-19 DOI: 10.1109/IWSOC.2004.1319892
D. Wiklund, S. Sathe, Dake Liu
{"title":"Network on chip simulations for benchmarking","authors":"D. Wiklund, S. Sathe, Dake Liu","doi":"10.1109/IWSOC.2004.1319892","DOIUrl":"https://doi.org/10.1109/IWSOC.2004.1319892","url":null,"abstract":"Networks are becoming increasingly popular for use as on-chip interconnects. The problems with specification and performance evaluation increase with these solutions compared to the traditional interconnect. This paper describes the design and simulation environment developed in the SoCBUS network-on-chip project. This environment is used as a basis to develop the benchmarking procedures necessary to assess the performance of the networks. Two benchmarking examples are presented and used for evaluation of the SoCBUS network. These examples show how the simulation environment can be used to find the load bottleneck. They also show the appropriateness of the SoCBUS solution for (hard) real-time systems.","PeriodicalId":306688,"journal":{"name":"4th IEEE International Workshop on System-on-Chip for Real-Time Applications","volume":"217 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-07-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121728048","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 34
SERDES technology for gigabit I/O communications in storage area networking 存储区域网络中用于千兆I/O通信的SERDES技术
4th IEEE International Workshop on System-on-Chip for Real-Time Applications Pub Date : 2004-07-19 DOI: 10.1109/IWSOC.2004.1319888
K. Iniewski, R. Badalone, M. Lapointe, M. Syrzycki
{"title":"SERDES technology for gigabit I/O communications in storage area networking","authors":"K. Iniewski, R. Badalone, M. Lapointe, M. Syrzycki","doi":"10.1109/IWSOC.2004.1319888","DOIUrl":"https://doi.org/10.1109/IWSOC.2004.1319888","url":null,"abstract":"The paper reviews SERDES technology for storage area networking. A concept of a data switch is introduced to illustrate important role played by switching and backplane SERDES ICs. Selected state-of-the-art devices: 10 Gb/s line side SERDES and backplane drivers are discussed in detail. Particular emphasis is placed on challenges associated with design of high-speed mixed-signal circuitry.","PeriodicalId":306688,"journal":{"name":"4th IEEE International Workshop on System-on-Chip for Real-Time Applications","volume":"98 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-07-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124899652","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Design of a comparator in CMOS SOI CMOS SOI比较器的设计
4th IEEE International Workshop on System-on-Chip for Real-Time Applications Pub Date : 2004-07-19 DOI: 10.1109/IWSOC.2004.1319884
Erik Säll, M. Vesterbacka
{"title":"Design of a comparator in CMOS SOI","authors":"Erik Säll, M. Vesterbacka","doi":"10.1109/IWSOC.2004.1319884","DOIUrl":"https://doi.org/10.1109/IWSOC.2004.1319884","url":null,"abstract":"This paper gives an introduction to the silicon-on-insulator (SOI) CMOS technology and presents the major advantages and disadvantages of using SOI. It also presents the design of a comparator, which has been sent for manufacturing, designed in a 0.13 /spl mu/m partially depleted SOI CMOS process. The comparator is a first step towards the design of a complete 6-bit flash analog-to-digital converter, with a sampling frequency of 1.5 GHz.","PeriodicalId":306688,"journal":{"name":"4th IEEE International Workshop on System-on-Chip for Real-Time Applications","volume":"71 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-07-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123036926","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
ECOMIPS: an economic MIPS CPU design on FPGA ECOMIPS:基于FPGA的经济型MIPS CPU设计
4th IEEE International Workshop on System-on-Chip for Real-Time Applications Pub Date : 2004-07-19 DOI: 10.1109/IWSOC.2004.1319896
Xizhi Li, Tiecai Li
{"title":"ECOMIPS: an economic MIPS CPU design on FPGA","authors":"Xizhi Li, Tiecai Li","doi":"10.1109/IWSOC.2004.1319896","DOIUrl":"https://doi.org/10.1109/IWSOC.2004.1319896","url":null,"abstract":"In recently years, many traditional ASIC applications are moving towards a more flexible FPGA based design. To establish a complete application system, it often needs a separate processor to achieve some interactive system functionalities such as I/O operations and control-sensitive tasks. Modern chip producers (Xilinx, Altera, etc) are promoting economic, yet powerful FPGA chips that have the capacity of migrating a general DSP or microprocessor into one FPGA chip. The trend is that both a general CPU module and the application specific circuit are to coexist on a single chip. This article introduces a MIPs CPU architecture or ECOMIPS to be implemented for that purpose. It focuses on economic resource utilization on modern chips (Xilinx Spartan 3 families). Traditional MIPs architecture was modified to avoid resource conflicts with the ASIC part. The key principles of designing such MIPs HDL IP cores are covered and analyzed with implementation results. As a second objective, ECOMIPS also tries to make itself a customizable and reusable architecture for bridging the gap between microprocessor and ASIC.","PeriodicalId":306688,"journal":{"name":"4th IEEE International Workshop on System-on-Chip for Real-Time Applications","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-07-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129704448","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 27
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