{"title":"SoC功能用于多处理器WCDMA基站调制解调器","authors":"R. Hobson, Allan R. Dyck, K. Cheung","doi":"10.1109/IWSOC.2004.1319901","DOIUrl":null,"url":null,"abstract":"WCDMA is a demanding 3rd generation wireless air interface technique. This paper discusses some system-on-chip architectural features associated with a fine-medium grain parallel DSP-based processor implementation of the base-band receiver section of a frequency division duplex WCDMA base-station. The software-oriented techniques are also relevant to other applications which require dense DSP.","PeriodicalId":306688,"journal":{"name":"4th IEEE International Workshop on System-on-Chip for Real-Time Applications","volume":"20 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2004-07-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"SoC features for a multi-processor WCDMA base-station modem\",\"authors\":\"R. Hobson, Allan R. Dyck, K. Cheung\",\"doi\":\"10.1109/IWSOC.2004.1319901\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"WCDMA is a demanding 3rd generation wireless air interface technique. This paper discusses some system-on-chip architectural features associated with a fine-medium grain parallel DSP-based processor implementation of the base-band receiver section of a frequency division duplex WCDMA base-station. The software-oriented techniques are also relevant to other applications which require dense DSP.\",\"PeriodicalId\":306688,\"journal\":{\"name\":\"4th IEEE International Workshop on System-on-Chip for Real-Time Applications\",\"volume\":\"20 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2004-07-19\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"4th IEEE International Workshop on System-on-Chip for Real-Time Applications\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IWSOC.2004.1319901\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"4th IEEE International Workshop on System-on-Chip for Real-Time Applications","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IWSOC.2004.1319901","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
SoC features for a multi-processor WCDMA base-station modem
WCDMA is a demanding 3rd generation wireless air interface technique. This paper discusses some system-on-chip architectural features associated with a fine-medium grain parallel DSP-based processor implementation of the base-band receiver section of a frequency division duplex WCDMA base-station. The software-oriented techniques are also relevant to other applications which require dense DSP.
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