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4th IEEE International Workshop on System-on-Chip for Real-Time Applications最新文献

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A scalable low-voltage extended swing CMOS LC quadrature VCO for RF transceivers 用于射频收发器的可扩展低压扩展摆幅CMOS LC正交压控振荡器
4th IEEE International Workshop on System-on-Chip for Real-Time Applications Pub Date : 2004-11-21 DOI: 10.1109/TENCON.2004.1414943
S. Hasan
{"title":"A scalable low-voltage extended swing CMOS LC quadrature VCO for RF transceivers","authors":"S. Hasan","doi":"10.1109/TENCON.2004.1414943","DOIUrl":"https://doi.org/10.1109/TENCON.2004.1414943","url":null,"abstract":"This paper describes a novel scalable low voltage CMOS folded-cascode QVCO (quadrature voltage controlled oscillator) design using the TSMC 0.18 /spl mu/m 5M1P CMOS process technology. The startup behavior of the proposed QVCO topology indicates that, the QVCO is free of bi-modal oscillation (frequency ambiguity). The VCO provided extended voltage swing with voltage supply scalable in the range 1.8V to 0.75V. The VCO operates in the range of 4GHz to 3GHz (corresponding to supply voltage scaling in the range 1.8V to 0.75V) with around 7% tuning range. The QVCO consumed under 5mW within the supply voltage scaling range. Phase noise simulations indicate a phase noise of around -165dBc/Hz at an offset of 600KHz from the carrier (@3.7GHz) for operation using the 1.8V supply voltage, which is quite favorable compared to other recent low-voltage QVCO designs.","PeriodicalId":306688,"journal":{"name":"4th IEEE International Workshop on System-on-Chip for Real-Time Applications","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126473177","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
FPGA implementation of fast radix 4 division algorithm 用FPGA实现快速基数4除法算法
4th IEEE International Workshop on System-on-Chip for Real-Time Applications Pub Date : 2004-07-19 DOI: 10.1109/IWSOC.2004.1319852
A. A. Ibrahem, H. Elsimary, A. Salama
{"title":"FPGA implementation of fast radix 4 division algorithm","authors":"A. A. Ibrahem, H. Elsimary, A. Salama","doi":"10.1109/IWSOC.2004.1319852","DOIUrl":"https://doi.org/10.1109/IWSOC.2004.1319852","url":null,"abstract":"The flexibility of field programmable gate arrays (FPGAs) can provide arithmetic intensive applications with the benefits of custom hardware but without the high cost of custom silicon implementations. In this paper, we present the adaptation of a fast radix 4 division algorithm (Srinivas and Parthi, 1994) for lookup table based FPGAs implementation. In this algorithm, the quotient digits are determined by observing three most-significant radix 2 digits of the partial remainder and independent of the divisor. The implementation has been done with Xilinx technology and FPGA-Advantage CAD tools.","PeriodicalId":306688,"journal":{"name":"4th IEEE International Workshop on System-on-Chip for Real-Time Applications","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-07-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123742577","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Integrating a single physical verification tool for systems-on-chip designs 为片上系统设计集成单一物理验证工具
4th IEEE International Workshop on System-on-Chip for Real-Time Applications Pub Date : 2004-07-19 DOI: 10.1109/IWSOC.2004.10002
J. Paris
{"title":"Integrating a single physical verification tool for systems-on-chip designs","authors":"J. Paris","doi":"10.1109/IWSOC.2004.10002","DOIUrl":"https://doi.org/10.1109/IWSOC.2004.10002","url":null,"abstract":"","PeriodicalId":306688,"journal":{"name":"4th IEEE International Workshop on System-on-Chip for Real-Time Applications","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-07-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121881857","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Evaluation of MP-SoC interconnect architectures: a case study 评估的MP-SoC互连架构:一个案例研究
4th IEEE International Workshop on System-on-Chip for Real-Time Applications Pub Date : 2004-07-19 DOI: 10.1109/IWSOC.2004.38
P. Pande, C. Grecu, M. Jones, A. Ivanov, R. Saleh
{"title":"Evaluation of MP-SoC interconnect architectures: a case study","authors":"P. Pande, C. Grecu, M. Jones, A. Ivanov, R. Saleh","doi":"10.1109/IWSOC.2004.38","DOIUrl":"https://doi.org/10.1109/IWSOC.2004.38","url":null,"abstract":"Multiprocessor (MP-SoC) platforms are emerging as the latest trend in SoC design. These MP-SoCs consist of a large number of IP blocks in the form of functionally heterogeneous embedded processors. In this design paradigm, IP blocks need to be integrated using a structured interconnect template, for example, according to high-performance parallel computing architectures. A formal evaluation process is required before adopting a specific parallel architecture to SoC domain. Here, we propose an evaluation methodology based on performance metrics that include latency, throughput and silicon area requirements. As a case study, we present the results of such an evaluation for two MP-SoC interconnect topologies, i.e., the mesh and the butterfly fat-tree (BFT). This evaluation methodology can be extended to any other SoC interconnect topology without loss of generality.","PeriodicalId":306688,"journal":{"name":"4th IEEE International Workshop on System-on-Chip for Real-Time Applications","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-07-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124966673","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
Beyond P-cell and gate-level: accuracy requirements for simulation of nanometer SoC design 超越P-cell和栅极级:纳米SoC设计仿真的精度要求
4th IEEE International Workshop on System-on-Chip for Real-Time Applications Pub Date : 2004-07-19 DOI: 10.1109/IWSOC.2004.1319843
B. Marshall
{"title":"Beyond P-cell and gate-level: accuracy requirements for simulation of nanometer SoC design","authors":"B. Marshall","doi":"10.1109/IWSOC.2004.1319843","DOIUrl":"https://doi.org/10.1109/IWSOC.2004.1319843","url":null,"abstract":"The forward march of Moore's law has resulted in integrated circuit (IC) design containing more and more functionality on a single chip. While nanometer technology enables expanded capability, such as analog-mixed signal system-on-chip (AMS SoC), it brings with it a new set of design closure problems. Complex designs demand more power and higher clock frequencies; they also create more signal and power net electromigration and substrate noise. The stress effect of a single analog device with unique diffusion measurements can cause an entire chip to fail. This is a huge problem for designers; half of all AMS designs fail first silicon. With mask costs reaching $1 million each, designers can no longer afford to rely on parameterized cell or gate-level parasitic extraction assumptions for analysis and simulation. Nanometer-era design require accurate and comprehensive data to enable accurate modeling.","PeriodicalId":306688,"journal":{"name":"4th IEEE International Workshop on System-on-Chip for Real-Time Applications","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-07-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126420833","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
10 GHz PLL using active shunt-peaked MCML gates and improved frequency acquisition XOR phase detector in 0.18 /spl mu/m CMOS 10 GHz锁相环，采用有源并联峰值MCML门和改进的频率采集异或鉴相器，采用0.18 /spl mu/m CMOS
4th IEEE International Workshop on System-on-Chip for Real-Time Applications Pub Date : 2004-07-19 DOI: 10.1109/IWSOC.2004.1319861
H. Bui, Y. Savaria
{"title":"10 GHz PLL using active shunt-peaked MCML gates and improved frequency acquisition XOR phase detector in 0.18 /spl mu/m CMOS","authors":"H. Bui, Y. Savaria","doi":"10.1109/IWSOC.2004.1319861","DOIUrl":"https://doi.org/10.1109/IWSOC.2004.1319861","url":null,"abstract":"When designing circuits operating at high frequencies, some design techniques are quite useful. Some recommended techniques include using MCML gate structures, simple structures, inductive loads and symmetric gates. By considering all these elements in the design process, a PLL working at speeds above 10 GHz has been realized in standard 0.18/spl mu/m CMOS process. In simulations, the PLL locked onto a reference clock with a period of 94 ps in little over 200 ns. This circuit was implemented and sent to TSMC for fabrication.","PeriodicalId":306688,"journal":{"name":"4th IEEE International Workshop on System-on-Chip for Real-Time Applications","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-07-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121714301","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
Integrated hardware-software platform for image processing applications 集成的硬件软件平台，用于图像处理应用
4th IEEE International Workshop on System-on-Chip for Real-Time Applications Pub Date : 2004-07-19 DOI: 10.1109/IWSOC.2004.42
T. Mohamed, Wael Badawy
{"title":"Integrated hardware-software platform for image processing applications","authors":"T. Mohamed, Wael Badawy","doi":"10.1109/IWSOC.2004.42","DOIUrl":"https://doi.org/10.1109/IWSOC.2004.42","url":null,"abstract":"This paper illustrates the design and implementation of an integrated hardware-software platform for image processing. This platform is versatile as it is configurable at run time, has low power consumption and requires minimal processing power from the host. Thus, the illustrated solution makes complex multimedia processing tasks feasible on handheld devices with low processing power and limited battery life. The concept is illustrated by a prototype system for image compression. The hardware part is an FPGA board that can be plugged into a standard PCMCIA socket on any portable system. The FPGA is configured at run time to perform block discrete cosine transforms (DCT). The software part running on the host computer is responsible for configuring the device at run time and sending chunks of input data and getting back the computed results. The design was tested successfully and performs 8*8 block DCT in 64 clock cycles running at 60MHz. An alternative hardware-efficient design using distributed arithmetic was also considered. The complete hardware/software prototype was integrated as a part of MPEG-4 encoder software.","PeriodicalId":306688,"journal":{"name":"4th IEEE International Workshop on System-on-Chip for Real-Time Applications","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-07-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132586685","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 18
Using integer equations to check PSL properties in RT level design 用整数方程检查RT电平设计中的PSL属性
4th IEEE International Workshop on System-on-Chip for Real-Time Applications Pub Date : 2004-07-19 DOI: 10.1109/IWSOC.2004.1319855
B. Alizadeh, Z. Navabi
{"title":"Using integer equations to check PSL properties in RT level design","authors":"B. Alizadeh, Z. Navabi","doi":"10.1109/IWSOC.2004.1319855","DOIUrl":"https://doi.org/10.1109/IWSOC.2004.1319855","url":null,"abstract":"This article describes a high level model of digital circuits for application of formal verification properties at this level. In our method, a behavioral state machine is represented by a multiplexer based structure of linear integer equations, and a subset of PSL property language is directly applied. It reduces the need for large BDD data structures and uses far less memory. Furthermore, there is no need to separate the data and control sections in circuits. We used a canonical form of linear TED (Ciesielski et al., 2002). This paper compares our results with those of the VIS verification tool which is a BDD based program.","PeriodicalId":306688,"journal":{"name":"4th IEEE International Workshop on System-on-Chip for Real-Time Applications","volume":"22 8","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-07-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132743085","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Design strategies for ESD protection in SOC SOC中ESD保护的设计策略
4th IEEE International Workshop on System-on-Chip for Real-Time Applications Pub Date : 2004-07-19 DOI: 10.1109/IWSOC.2004.1319880
K. Iniewski, V. Axelrad, A. Shibkov, A. Balasinski, M. Syrzycki
{"title":"Design strategies for ESD protection in SOC","authors":"K. Iniewski, V. Axelrad, A. Shibkov, A. Balasinski, M. Syrzycki","doi":"10.1109/IWSOC.2004.1319880","DOIUrl":"https://doi.org/10.1109/IWSOC.2004.1319880","url":null,"abstract":"Design strategies for efficient ESD protection in system-on-chip (SOC) integrated circuits are discussed. Various options for power clamp and I/O ESD architectures are considered. Multiple ESD protection circuits with feedback triggering have been analyzed using physical mixed-mode circuit-device simulation, utilizing finite element models for MOSFETs.","PeriodicalId":306688,"journal":{"name":"4th IEEE International Workshop on System-on-Chip for Real-Time Applications","volume":"182 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-07-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124566191","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
MPEG-4 FGS encoder design for an interactive content-aware MPEG-4 video streaming SOC 交互式内容感知MPEG-4视频流SOC的MPEG-4 FGS编码器设计
4th IEEE International Workshop on System-on-Chip for Real-Time Applications Pub Date : 2004-07-19 DOI: 10.1109/IWSOC.2004.1319873
Yung-Chi Chang, Chih-Wei Hsu, Liang-Gee Chen
{"title":"MPEG-4 FGS encoder design for an interactive content-aware MPEG-4 video streaming SOC","authors":"Yung-Chi Chang, Chih-Wei Hsu, Liang-Gee Chen","doi":"10.1109/IWSOC.2004.1319873","DOIUrl":"https://doi.org/10.1109/IWSOC.2004.1319873","url":null,"abstract":"In this paper, the computational complexity of MPEG-4 fine granularity scalability (FGS) coding is analyzed to explore an efficient FGS implementation for video streaming applications. With the proposed hardware-oriented optimization approaches, a hardwired FGS block-level processing core is proposed to provide a cost-effective solution. It can be integrated into an existing MPEG-4 coding system to form an interactive video streaming system. By the proposed FGS coder with reordered coding flow, the streaming server can adaptively decide quality-enhanced region by selective enhancement according to both object information from encoding side and user-defined region from receiver side. The proposed hardware core can support FGS profile level 5, frame size 720x576, 30Hz, for real-time streaming applications at 54 MHz.","PeriodicalId":306688,"journal":{"name":"4th IEEE International Workshop on System-on-Chip for Real-Time Applications","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-07-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117326774","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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