K. Iniewski, V. Axelrad, A. Shibkov, A. Balasinski, M. Syrzycki
{"title":"SOC中ESD保护的设计策略","authors":"K. Iniewski, V. Axelrad, A. Shibkov, A. Balasinski, M. Syrzycki","doi":"10.1109/IWSOC.2004.1319880","DOIUrl":null,"url":null,"abstract":"Design strategies for efficient ESD protection in system-on-chip (SOC) integrated circuits are discussed. Various options for power clamp and I/O ESD architectures are considered. Multiple ESD protection circuits with feedback triggering have been analyzed using physical mixed-mode circuit-device simulation, utilizing finite element models for MOSFETs.","PeriodicalId":306688,"journal":{"name":"4th IEEE International Workshop on System-on-Chip for Real-Time Applications","volume":"182 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2004-07-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"Design strategies for ESD protection in SOC\",\"authors\":\"K. Iniewski, V. Axelrad, A. Shibkov, A. Balasinski, M. Syrzycki\",\"doi\":\"10.1109/IWSOC.2004.1319880\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Design strategies for efficient ESD protection in system-on-chip (SOC) integrated circuits are discussed. Various options for power clamp and I/O ESD architectures are considered. Multiple ESD protection circuits with feedback triggering have been analyzed using physical mixed-mode circuit-device simulation, utilizing finite element models for MOSFETs.\",\"PeriodicalId\":306688,\"journal\":{\"name\":\"4th IEEE International Workshop on System-on-Chip for Real-Time Applications\",\"volume\":\"182 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2004-07-19\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"4th IEEE International Workshop on System-on-Chip for Real-Time Applications\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IWSOC.2004.1319880\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"4th IEEE International Workshop on System-on-Chip for Real-Time Applications","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IWSOC.2004.1319880","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Design strategies for efficient ESD protection in system-on-chip (SOC) integrated circuits are discussed. Various options for power clamp and I/O ESD architectures are considered. Multiple ESD protection circuits with feedback triggering have been analyzed using physical mixed-mode circuit-device simulation, utilizing finite element models for MOSFETs.
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