{"title":"Integrating a single physical verification tool for systems-on-chip designs","authors":"J. Paris","doi":"10.1109/IWSOC.2004.10002","DOIUrl":null,"url":null,"abstract":"","PeriodicalId":306688,"journal":{"name":"4th IEEE International Workshop on System-on-Chip for Real-Time Applications","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2004-07-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"4th IEEE International Workshop on System-on-Chip for Real-Time Applications","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IWSOC.2004.10002","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}