K. Iniewski, R. Badalone, M. Lapointe, M. Syrzycki
{"title":"SERDES technology for gigabit I/O communications in storage area networking","authors":"K. Iniewski, R. Badalone, M. Lapointe, M. Syrzycki","doi":"10.1109/IWSOC.2004.1319888","DOIUrl":null,"url":null,"abstract":"The paper reviews SERDES technology for storage area networking. A concept of a data switch is introduced to illustrate important role played by switching and backplane SERDES ICs. Selected state-of-the-art devices: 10 Gb/s line side SERDES and backplane drivers are discussed in detail. Particular emphasis is placed on challenges associated with design of high-speed mixed-signal circuitry.","PeriodicalId":306688,"journal":{"name":"4th IEEE International Workshop on System-on-Chip for Real-Time Applications","volume":"98 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2004-07-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"4th IEEE International Workshop on System-on-Chip for Real-Time Applications","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IWSOC.2004.1319888","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 4
Abstract
The paper reviews SERDES technology for storage area networking. A concept of a data switch is introduced to illustrate important role played by switching and backplane SERDES ICs. Selected state-of-the-art devices: 10 Gb/s line side SERDES and backplane drivers are discussed in detail. Particular emphasis is placed on challenges associated with design of high-speed mixed-signal circuitry.