Formal verification of digital circuits

Abstract

For more than two decades formal verification of digital circuits is a hot research topic and in the last ten years this technology finds its way in the industry where EDA companies have produced a number of efficient tools. This tutorial covers the various techniques used to verify the correctness of combinational and sequential circuits. Also, the verification of properties using model checking will be discussed. The topics covered in the tutorial are: HDL based verification, Binary Decision Diagrams (BDD), SAT solvers, Theorem provers, Combinational Equivalence Checkers, Miter Circuit, SAT / BDD partitioning, Finite State Machine traversal algorithms, Model Checking.