{"title":"A model for a reusable system-on-a-chip hardware component integrated with design exploration methodology","authors":"A. M. Sllame","doi":"10.1109/IWSOC.2004.1319895","DOIUrl":"https://doi.org/10.1109/IWSOC.2004.1319895","url":null,"abstract":"This paper presents a proposal for reusable hardware core (component) model. The model is designed based on the knowledge gained by the exploiting the design space exploration methodology presented in (Sllame, 2003). The model structure contains component characterization, computation core specified in VHDL language, a test bench to smooth the component integration process within the application and interfacing.","PeriodicalId":306688,"journal":{"name":"4th IEEE International Workshop on System-on-Chip for Real-Time Applications","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-07-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128702776","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"High-speed I/Os and PLLs for data communication applications","authors":"K. Iniewski, S. Mirabbasi","doi":"10.1109/IWSOC.2004.10008","DOIUrl":"https://doi.org/10.1109/IWSOC.2004.10008","url":null,"abstract":"The wireline communication industry is working on the communication systems with data rates of beyond 10 Gb/s. Mixed-signal circuits are required to transmit and receive Gb/s signals over high-speed serial interfaces, and to synthesize and recover GHz clocks, typically using phase-locked loop circuitry. This tutorial will start with setting up a system environment for high-speed serial link applications. Long-haul and metropolitan area networks undergoing transition from OC-48 (2.488 Gb/s) to OC-192 (9.953 Gb/s or 10.7 Gb/s using forward error correction) will be discussed. Upgrades of local area networks (LANs) from 1.25 Gb/s to 10.3 Gb/s Ethernet I/Os are mentioned. Movement of disk drives and storage area networks (SANs) to 10.5 Gb/s Fibre Channel interfaces is described. A brief overview of chip to chip data transfer schemes follows, with an emphasis on the serial I/O. Then fundamentals of phase-locked loop (PLL) design will be discussed. First, the overall system specification for (charge-pump based) PLL systems is presented. Openand closed-loop PLL transfer functions are briefly reviewed. Loop stability and jitter sources are discussed. Design issues for circuit blocks like voltagecontrolled oscillators (VCOs), phase-frequency detectors (PFDs) and charge pumps are discussed. Key PLL based systems, e.g., Clock Synchronizer and Clock/Data Recovery (CDR), are described. The tutorial ends with discussion and design issues of output driver and receiver input blocks of serial links. Pre-emphasis and equalization concepts are described. Implementation schemes for I/O termination and ESD protection are discussed.","PeriodicalId":306688,"journal":{"name":"4th IEEE International Workshop on System-on-Chip for Real-Time Applications","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-07-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130711047","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Victor H. S. Ha, S. Choi, J. Jeon, G. Lee, Won-Kap Jang, Woosung Shim
{"title":"Real-time audio/video decoders for digital multimedia broadcasting","authors":"Victor H. S. Ha, S. Choi, J. Jeon, G. Lee, Won-Kap Jang, Woosung Shim","doi":"10.1109/IWSOC.2004.1319871","DOIUrl":"https://doi.org/10.1109/IWSOC.2004.1319871","url":null,"abstract":"A new national standard for digital multimedia broadcasting (DMB) has been drafted in Korea to provide high quality digital audio, video, and data broadcasting services to fixed, mobile, and portable receivers. We have developed the world's first DSP/FPGA implementation of the portable DMB receiver, complete with an RF receiver, a 6.4-inch LCD display, and audio/video/data decoders. In this paper, we present the design, implementation, and performance of this portable DMB receiver. First, we provide a brief overview of the DMB system and the audio/video coding tools supported by it, i.e., MPEG-4 BSAC and MPEG-4 Part 10 AVC/H.264. We discuss the low-power high-performance design of the DMB receiver, focusing particularly on the audio/video decoding parts. Finally, we illustrate the performance of the portable DMB receiver that operates in real-time at the overall frequency of 25 MHz.","PeriodicalId":306688,"journal":{"name":"4th IEEE International Workshop on System-on-Chip for Real-Time Applications","volume":"21 12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-07-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128453600","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Interconnect synthesis for systems on chip","authors":"N. Bambha, S. Bhattacharyya","doi":"10.1109/IWSOC.2004.44","DOIUrl":"https://doi.org/10.1109/IWSOC.2004.44","url":null,"abstract":"We describe an algorithm for performing a joint scheduling/interconnect synthesis optimization for system-on-chip (SoC) architectures. The algorithm is able to account for different distributions of long vs. short interconnect routes in an architecture. It is based on a genetic algorithm, and utilizes a graph isomorphism test to significantly pare the search space and increase the search efficiency.","PeriodicalId":306688,"journal":{"name":"4th IEEE International Workshop on System-on-Chip for Real-Time Applications","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-07-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127739376","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A 2-D forward/inverse integer transform processor of H.264 based on highly-parallel architecture","authors":"Ling Liu, Lin Qiu, Meng-tian Rong, Jiang Li","doi":"10.1109/IWSOC.2004.1319870","DOIUrl":"https://doi.org/10.1109/IWSOC.2004.1319870","url":null,"abstract":"A design of 2-D forward and inverse integer transform processor is presented, which is suitable for MPEG-4 AVC/H.264 visual profile. The comparability between the forward and inverse transform and the symmetry of their arithmetic has been utilized in architecture. According to this design, 2-D transform is implemented by using duplicated 1-D transform. Parallel register array are used to realize the transpose operation. Under 0.35um technology, the logic gate count is only 3524 when the maximum frequency is more than 120MHz.","PeriodicalId":306688,"journal":{"name":"4th IEEE International Workshop on System-on-Chip for Real-Time Applications","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-07-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126566646","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Automated fixing of complex/process critical DRC violations in place and route systems using calibre in the synopsys/milkyway environment","authors":"V. Lakshmanan","doi":"10.1109/IWSOC.2004.10006","DOIUrl":"https://doi.org/10.1109/IWSOC.2004.10006","url":null,"abstract":"With the proliferation of analog/mixed signal SoCs, physical verification has become the critical link not only at the cell/block and full-chip levels, but also between design styles. It is equally critical for successful data transfer between and within semiconductor companies, and providers of library components, external IP, internal IP and design services. Adopting a single, robust, hierarchical-based physical verification tool not only streamlines the design flow, it saves the time and cost of supporting multiple tools, eliminates the discrepancies created by the differences between tools, and ensures successful data transfer. This tutorial will demonstrate how a single physical verification tool can be easily integrated throughout the design flow, across design styles and within popular design frameworks.","PeriodicalId":306688,"journal":{"name":"4th IEEE International Workshop on System-on-Chip for Real-Time Applications","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-07-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131350145","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A step towards intelligent translation from high-level design to RTL","authors":"J. David, E. Bergeron","doi":"10.1109/IWSOC.2004.1319875","DOIUrl":"https://doi.org/10.1109/IWSOC.2004.1319875","url":null,"abstract":"Many researches have progressed to elaborate high level languages for system design. Nevertheless automatic refinement from high level to RTL can still not be automated and if designers can now specify their system at a high level, they are still forced to manually implement its RTL representation or use IP. We have developed an intermediate level language based on the representation of ASM charts with extensions such as user defined operators, communication channels, generic calls and recursivity but near the RTL level. This paper describes our compiler and presents our latest compilation results: the recursive \"Towers of Hanoi\" algorithm, various sort algorithms (included quick sort) and a mix of heap and merge sorts to implement fast parallel sort. These algorithms have been automatically synthesized in a FPGA and offer one to three orders of magnitude improvement compared to a pure software implementation for NoC. The tool is easily accessible to software or hardware designers and people from both communities will appreciate its high-level and cycle accurate approach.","PeriodicalId":306688,"journal":{"name":"4th IEEE International Workshop on System-on-Chip for Real-Time Applications","volume":"231 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-07-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120958348","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A field programmable bit-serial digital signal processor","authors":"S. A. Rahim, L. Turner","doi":"10.1109/IWSOC.2004.1319897","DOIUrl":"https://doi.org/10.1109/IWSOC.2004.1319897","url":null,"abstract":"The field programmable digital signal processor (FPDSP) architecture is intended to allow application specific DSP filtering at moderate sample rates where the ability to rapidly modify the filter characteristics can be used to an advantage. Applications that the FPDSP will be best suited for are rapid prototyping of filters, audio applications, and to evaluate the potential advantages of run-time reconfiguration. The system architecture is based on an input pipelined least significant bit first bit-serial two's complement arithmetic. It performs digital signal processing by using programmable bit-serial signal processing units and programmable interconnect. The bit-serial processing units implement simple arithmetic operations: summation, multiplication and division by powers of two, and multiplication by negative one. The programmable unit also has variable bit-delays to time-align bit-serial words and also generates the control signals for the arithmetic operations internally. By combining the functions of these programmable units, a 2nd order recursive filter has been built and tested to verify the functionality of the FPDSP.","PeriodicalId":306688,"journal":{"name":"4th IEEE International Workshop on System-on-Chip for Real-Time Applications","volume":"160 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-07-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133173154","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A customizable embedded SoC platform architecture","authors":"P. Nsame, Y. Savaria","doi":"10.1109/IWSOC.2004.1319898","DOIUrl":"https://doi.org/10.1109/IWSOC.2004.1319898","url":null,"abstract":"In this paper, we present a general purpose and customizable IP platform, with hardware support for multiprocessors, multithreading and real-time applications. It integrates essential elements of a scalable SoC software and hardware architecture. The communication structure is based on virtual channels. As a result, the latencies across the software and hardware resources are significantly reduced. We use queues to communicate between functional units (or IP cores) in order to facilitate timing closure and verification.","PeriodicalId":306688,"journal":{"name":"4th IEEE International Workshop on System-on-Chip for Real-Time Applications","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-07-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125005510","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
T. Lindkvist, J. Löfvenberg, H. Ohlsson, K. Johansson, L. Wanhammar
{"title":"A power-efficient, low-complexity, memoryless coding scheme for buses with dominating inter-wire capacitances","authors":"T. Lindkvist, J. Löfvenberg, H. Ohlsson, K. Johansson, L. Wanhammar","doi":"10.1109/IWSOC.2004.1319890","DOIUrl":"https://doi.org/10.1109/IWSOC.2004.1319890","url":null,"abstract":"In this paper we present a simplified model of parallel, on-chip buses, motivated by the movement toward CMOS technologies where the ratio between interwire capacitance and wire-to-ground capacitance is very large. We also introduce a ternary bus state representation, suitable for the bus model. Using this representation we propose a coding scheme without memory which reduces energy dissipation in the bus model by approximately 20-30% compared to an uncoded system. At the same time the proposed coding scheme is easy to realize, in terms of standard cells needed, compared to several previously proposed solutions.","PeriodicalId":306688,"journal":{"name":"4th IEEE International Workshop on System-on-Chip for Real-Time Applications","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-07-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130428781","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}